Systran SCRAMNet+ VME3U, Hardware Reference Manual

Page: 40 / 134

OPERATION
Copyright 1995, S
YS
I
RAN
Corp. 4-14 VME3U H/W REFERENCE
4.7.2 Network Error
The second interrupt condition is designed to intercept network errors. CSR1 contains the
following error conditions which may be masked by CSR9:
Table 4-5 Interrupt Error Conditions
Bit Interrupt
0 Transmit FIFO Full
1 Transmit FIFO Not Empty
2
Transmit FIFO
O
Full
3 (Not masked for errors)
4 Interrupt FIFO Full
5 Protocol Violation
6 Carrier Detect Failure
7 Bad Message
8 Receiver Overflow
9 Transmit Retry
10 Transmit Retry Time-out
11 Redundant Rx/Tx Fault
12 General Purpose Counter/Timer
13 (Not masked for errors)
14 (Not masked for errors)
15 Fiber Optic Bypass Not Connected
Each of these conditions is identified by the corresponding bit being set (value 1) in
CSR1. If any of the preceding conditions are set and the Interrupt On Memory Mask
Match Enable (CSR0, bit 5) is set, then an interrupt will be generated to the host
computer. Additional information about each error condition is contained in Section 5,
Table 5-2: CSR1.
If a Network Error is received (Figure 4-3), and if Interrupt on Error (CSR0, bit7) and
Host Interrupt Enable (CSR0, bit 3) are set, and Interrupts are Enabled (CSR1, bit 14),
then the message generates an interrupt to the host. If additional network data interrupts
occur before the processor is able to service the interrupt, those shared-memory locations
are updated and the addresses are added to the Interrupt FIFO queue. However, no
additional interrupt signals are sent to the host until interrupts are armed by writing to
CSR1.
There must also be an interrupt vector to the Interrupt Service Routine. The data vector is
stored in CSR6, and the error vector is in CSR7. CSR6 is associated with a memory
update and CSR7 is used to identify an error interrupt. Details are included in the
Programmer’s Reference Guide (
Doc. Nr. C-T-MR-PROGREF#-A-0-A2
).