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APPENDIX D

HOST ACCESS TIMING

TABLE OF CONTENTS

D.1 Introduction ........................................................................................................................... D-1

D.2 Dual-Port RAM Controller Module....................................................................................... D-1

D.2.1 Contention ................................................................................................................... D-1

D.3 Host Interface Logic to Shared Memory/CSR ....................................................................... D-2

D.3.1 ASIC-Internal CSR READ .......................................................................................... D-2

D.3.2 ASIC-Internal CSR WRITE ........................................................................................ D-3

D.4 Host Interface Logic to Host Specific CSR ........................................................................... D-4

D.4.1 Host-Specific CSR READ........................................................................................... D-4

D.5 Access Times......................................................................................................................... D-5

D.5.1 Typical Access Sequence ............................................................................................ D-5

D.5.2 Worst-Case Condition ................................................................................................. D-6

D.5.3 Back-to-Back Host READs ......................................................................................... D-7

D.5.4 Back-to-Back Host WRITEs ....................................................................................... D-9

Summary of Contents for SCRAMNet+ VME3U

Page 1: ...SCRAMNet Network VME3U Hardware Reference Document No D T MR VME3U A 0 A2...

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Page 3: ...inted material including but not limited to the implied warranties of merchantability and fitness for a particular purpose Copyright 1995 SYSTRAN Corporation All rights reserved SCRAMNet is a register...

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Page 5: ...7 1 SCRAMNet Diagnostics 2 4 2 7 2 EEPROM Initialization EPI 2 4 2 7 3 SCRAMNet Monitor 2 4 3 0 DESCRIPTION 3 1 3 1 Overview 3 1 3 2 Shared Memory 3 1 3 2 1 Dual Port Memory Controller 3 1 3 2 2 Contr...

Page 6: ...Interrupt Handling 4 15 4 8 External Triggers 4 15 4 9 General Purpose Counter Timer 4 15 4 9 1 Available Modes 4 16 4 9 2 Rollover Reset 4 16 4 9 3 Presetting Values 4 16 4 10 Modes of Operation 4 1...

Page 7: ...Figure 4 7 Mechanical Switch Loopback Mode 4 22 Figure 4 8 Fiber Optic Loopback Mode 4 24 Figure 4 9 Insert Mode 4 25 Figure 4 10 Quad Switch 4 26 Figure 4 11 Interrupt Service Routine 4 28 Figure 6...

Page 8: ...ol Register 5 12 Table 5 10 CSR9 SCRAMNet Interrupt On Error Mask 5 13 Table 5 11 CSR10 SCRAMNet Shared Memory Address LSW 5 14 Table 5 12 CSR11 SCRAMNet Shared Memory Address MSW 5 14 Table 5 13 CSR1...

Page 9: ...overview of the SCRAMNet VME3U product and host interface compatibility Description A functional description of the SCRAMNet network node Installation Procedures for unpacking configuring and installi...

Page 10: ...ssary of words phrases and terms used in the reference manual 1 4 Related Documentation SCRAMNet Network Utilities User Manual Doc Nr C T MU UTIL A 0 A1 A user s manual for the SCRAMNet Classic SCRAMN...

Page 11: ...s memory RAM Installing any memory upgrade overrides the on board 128 KB memory 2 1 1 Network Features A ring topology with 150 Mbit s line transmission rate A Data Filter that allows only data stored...

Page 12: ...nodes or sub rings eliminates the need for a separate Fiber Optic Bypass and functions as a repeater 2 1 3 VME3U Board Features Mezzanine board memory upgrade option General Purpose Counter Error Inte...

Page 13: ...ransfers to the shared memory on the SCRAMNet VME3U host interface can be 8 or 16 bits wide and may be of the read modify write type If the host needs to pass 32 bit data to shared memory it must be a...

Page 14: ...oard or a SCRAMNet LX SCRAMNet board and adjust the test menus accordingly 2 7 2 EEPROM Initialization EPI The EEPROM Initialization program is a SCRAMNet utility used to simplify configuration of the...

Page 15: ...n the network This is why it is also referred to as replicated shared memory A good analogy is the COMMON AREA used by the FORTRAN programming language Where the COMMON AREA makes variables available...

Page 16: ...N NODE OUT All Reads All Writes P1 ASIC Host Interface Logic Replicated Shared Memory Interrupt FIFO Network Control Logic Tranceiver FIFO Receiver Transmitter Transmitt FIFO Dual Port Memory Controll...

Page 17: ...dition indicator CSR1 bit 2 ON When the Transmit FIFO reaches a FULL condition CSR1 bit 0 ON one more host WRITE could cause a message to be lost To prevent this the CSR controllable built in SCRAMNet...

Page 18: ...a must be passed very rapidly When the node operates in BURST or BURST PLUS mode the node will never re transmit its own messages for error correction When operating in PLATINUM or PLATINUM PLUS mode...

Page 19: ...or interrupt action s are to be taken whenever writing to any byte of the SCRAMNet shared memory 4 byte word Only five bits of the ACR are associated with every four byte word of shared memory on eve...

Page 20: ...ry locations may also be used to generate signals to external triggers The procedure for selecting shared memory locations for interrupts and or external triggers is explained in the paragraph on the...

Page 21: ...NETWORK LOGIC RING Address Data OUTGOING A22 A0 D31 D0 TIE D31 D0 A22 A0 D31 D0 1 Figure 3 3 Outgoing Interrupt INCOMING INTERRUPT CPU INTERRUPT FIFO ACR SHARED MEMORY Address Address Data Interrupt B...

Page 22: ...rrupt bit When Override Transmit Interrupt Enable CSR0 bit 9 is set an interrupt will be sent out on the network regardless of the status of the ACR Transmit Interrupt bit A third condition Receive In...

Page 23: ...tted to the network EXAMPLE If location 1000 in SCRAMNet memory contains the value 20 and the host processor writes the value 20 to location 1000 then no network traffic will be generated However if a...

Page 24: ...t READ on that longword boundary On the next READ operation not the same location or within the same longword boundary the remaining data is provided 3 10 3 VME Holdoff Mode It is possible that the Tr...

Page 25: ...Loopback mode when the node is in use as a part of the network This configuration is not a substitute for the Fiber Optic Bypass Switch for network operation 3 10 5 Write Me Last Mode The Write Me Las...

Page 26: ...h cabinet Port 5 access is at the rear of the cabinet All 5 ports have standard SCRAMNet transmitters and receivers Each port can transmit data to and receive data from the internal ring The Quad Swit...

Page 27: ...riven applications an interrupt service routine ISR is required to handle the interrupts triggered by the SCRAMNet node An example of a generic ISR is included Figure 4 11 page 4 28 at the end of this...

Page 28: ...memory at 4 MB Any WRITE accesses to the lower 4 MB will be ignored since there is no memory addressed there 4MB 6MB 8MB 0 2MB Node 1 Node 3 Node 5 Node 7 Node 9 Node 2 Node 4 Node 6 Node 8 4MB 4MB 2...

Page 29: ...MNet memory common blocks should be declared to be sized to an integer multiple of the processor memory page size If this is not done most compilers will try to optimize memory usage by filling out th...

Page 30: ...nt and SCRAMNet memory is available for access The memory address will remain at 0 and be disabled until programmed with the EEPROM Initialization Program NOTE All SCRAMNet nodes in the fiber optic ne...

Page 31: ...s 21 bit A 22 2 field contains the relative SCRAMNet memory address Bits A0 and A1 are always zero for a longword boundary DATA VALUE This 32 bit field contains the data value of the word in SCRAMNet...

Page 32: ...board at a rate greater than or equal to 16 7 MB sec this is a 32 bit WRITE every 240 ns Any delay in the host data WRITE will result in failure of step 1 and a premature end to the PLUS mode transmi...

Page 33: ...odes are transmitting in the BURST mode the network data passing through the other nodes can affect that node s output performance If a node s receiver is so busy that the Transceiver FIFO is never em...

Page 34: ...ACR values to take effect for interrupt action the following SCRAMNet CSR actions should be considered for the type of interrupt operation desired Host Interrupt Enable to receive network interrupts N...

Page 35: ...n interrupt request as specified in the CSR9 Mask register Network Interrupt Enable CSR0 8 Permits transmission of interrupt data to the network Override TIE CSR0 9 Interrupt will be transmitted to th...

Page 36: ...CSR0 to 81AB hex if you wish to enable interrupt on errors SEND RECEIVE WITHOUT INTERRUPTS Set CSR0 to F000 hex to insert the node and initiate the reset of the FIFOs Set CSR0 to 8003 hex to insert t...

Page 37: ...ACR TIE HOST WRITE OVERRIDE TIE NETWORK INTERRUPT ENABLE TRANSMIT INTERRUPT SLOT TO NETWORK TRANSMIT NON INTERRUPT SLOT TO NETWORK CSR0 BIT 9 CSR0 BIT 8 NO NO ACR BIT 1 YES YES YES NO TRANSMIT ENABLE...

Page 38: ...errupts These shared memory locations may also be used to generate signals to external triggers The procedure for selecting shared memory locations for interrupts and or external triggers is explained...

Page 39: ...MATCH ENB ACR RIE OVERRIDE RIE ENB INT ON Rx IN OWN SLOT WRITE OWN SLOT ENB INT ON ERRORS RECEIVE ENABLE CSR0 BIT 0 MUST BE ACTIVE NO YES YES NO YES NO YES NO NO YES NO YES NO NO NO YES YES YES INTER...

Page 40: ...mory Mask Match Enable CSR0 bit 5 is set then an interrupt will be generated to the host computer Additional information about each error condition is contained in Section 5 Table 5 2 CSR1 If a Networ...

Page 41: ...ork interrupt Every READ of CSR5 and CSR4 will automatically increment the FIFO pointer to the next interrupt address for both registers CSR4 should be read only if Interrupt FIFO Not Empty CSR5 bit 1...

Page 42: ...clear the counter 4 9 2 Rollover Reset A rollover reset can generate an interrupt if selected to do so from the error mask register CSR9 bit 12 When this bit is set whenever the counter register CSR 1...

Page 43: ...bit transactions will occur on the bus each requiring a SCRAMNet network WRITE The HIPRO mode was created to provide an efficient means to transmit two 16 bit data transactions as one 32 bit network...

Page 44: ...995 SYSIRAN Corp 4 18 VME3U H W REFERENCE DATA FILTER LOGIC DO NOTHING YES SAME WRITE TO MEMORY NEW DATUM OLD DATUM NO READ WRITE HOST CPU SHARED MEMORY NETWORK RING NETWORK LOGIC NETWORK RING Figure...

Page 45: ...not the same location within the same longword boundary the remaining data is provided without issuing another READ to shared memory 4 10 3 Loopback Modes Each node has a Monitor and Bypass mode Wire...

Page 46: ...twork data is not re transmitted Table 4 7 Monitor and Bypass Mode States State Register Setting Receive Enable CSR0 bit 0 ON Transmit Enable CSR0 bit 1 OFF Insert Enable CSR0 bit 15 OFF Enable Wire L...

Page 47: ...ifications to work In this mode the transmitted signal does not leave the board Table 4 8 Wire Loopback Mode States State Register Setting Receive Enable CSR0 bit 0 OFF Transmit Enable CSR0 bit 1 OFF...

Page 48: ...Card Table 4 9 Mechanical Switch Loopback Mode States State Register Setting Receive Enable CSR0 bit 0 ON Transmit Enable CSR0 bit 1 ON Insert Enable CSR0 bit 15 ON Enable Wire Loopback CSR2 bit 7 OF...

Page 49: ...and the receiver is disconnected from the network Table 4 10 Fiber Optic Loopback Mode States State Register Setting Receive Enable CSR0 bit 0 ON Transmit Enable CSR0 bit 1 ON Insert Enable CSR0 bit 1...

Page 50: ...network However this configuration could not be used in a network ring in the place of a Fiber Optic Bypass Switch because it would cause a break in ring continuity 4 10 4 Node Insert Mode In this mo...

Page 51: ...matically slows down CPU data WRITEs to the SCRAMNet memory when the Transmit FIFO becomes full The Transmit FIFO serves as a buffer between the SCRAMNet memory and the SCRAMNet network The Transmit F...

Page 53: ...s the Disable Host to Shared Memory Write 4 11 Quad Switch The Quad Switch is a switching center and is used to dynamically configure active SCRAMNet and SCRAMNet ring s The Quad Switch provides dynam...

Page 54: ...or will be invoked Interrupts will be disabled until re armed by writing to CSR1 Until that time all other interrupts will be written into the Interrupt FIFO where they can be processed in the Interru...

Page 55: ...gister and the function of each bit The name of each bit is indicative of its set state The registers are described using bit 0 as the Least Significant Bit LSB For example Inserting A7C3 hex in a 16...

Page 56: ...it Only or Transmit Receive the Transmit FIFO should be cleared If not all buffered transmit messages will be sent out on the network 10 Transmit Only In this mode any received message bypasses the sh...

Page 57: ...ed memory location ACR bit 3 External Trigger 2 Setting this bit will generate a trigger signal to an external connector whenever there is a network WRITE to this shared memory location ACR bit 4 HIPR...

Page 58: ...speed holding area for data flowing through the network NOTE If the R T FIFO were to be reset during active network transmissions the data in the FIFO at that time would be lost and it would cause er...

Page 59: ...n to OFF 5 Protocol Violation Latched When this bit is ON there has been a signal error at the physical layer fiber or coax resulting from noise on the transmission lines or a result of hardware failu...

Page 60: ...me network events free run 26 66 ns and free run 1 706 ns with trigger 2 CLEAR 13 Current Link Latched This bit tells which of the optional redundant transceivers is currently selected as the active l...

Page 61: ...network The purpose of this bit is purely diagnostic This mode is valid only when the Insert Node CSR0 bit 15 is OFF 8 Disable Host to Memory Write When this bit is set the host WRITEs are not written...

Page 62: ...be written to the network HIPRO will not work when Disable Host to Memory WRITE CSR2 bit 8 is set 14 Multiple Messages This bit allows multiple native messages on the network It is used in conjunction...

Page 63: ...t Table 5 5 CSR4 Bits Interrupt Address LSP READ ONLY 15 0 LSP of the Interrupt Address These bits represent the LSP of the interrupt address A15 A0 Bits 0 and 1 are always 0 since the addresses are o...

Page 64: ...ster must be pre loaded with the vector before interrupt processing can occur 15 0 Reserved Table 5 8 CSR7 Bits External Control Status Register READ WRITE 7 0 Interrupt Vector This host specific regi...

Page 65: ...ill cause the GPC to free run at a rate of 37 5 MHz 26 66 ns This counter mode overrides all other counter mode settings 10 Receive Interrupt Override When this bit is set all incoming network message...

Page 66: ...sk 6 Carrier Detect Fail Mask 7 Bad Message Mask 8 Receiver Overflow Mask 9 Transmitter Retry Mask 10 Transmitter Retry Due to Time Out Mask 11 Redundant TX RX Fault Mask 12 Interrupt on General Purpo...

Page 67: ...dress Enable This bit enables the on ASIC comparator for shared memory access 11 1 0 Always zero 12 SMA12 13 SMA13 Shared Memory Address 14 SMA14 15 SMA15 Table 5 12 CSR11 Bits SCRAMNet Replicated Sha...

Page 68: ...rtual Paging Enable When ON this bit enables Virtual Paging 4 1 0 Always zero 5 VP_A12 6 VP_A13 7 VP_A14 8 VP_A15 9 VP_A16 Virtual Page number The significance of this register is dependent on the 10...

Page 69: ..._COUNT 2 3 RD_COUNT 3 4 RD_COUNT 4 5 RD_COUNT 5 6 RD_COUNT 6 This is a General Purpose Counter Timer register It can be used to 7 RD_COUNT 7 count trigger 1 and 2 events count errors or other events a...

Page 70: ...ster that holds the VME Interrupt Priority Level IRQ Bits reflect the Interrupt Priority Level For example IPL 5 translates to setting bit 5 20 hex Selector Chart Level Bit Hex 7 6 5 4 3 2 1 1 0 0 0 0...

Page 71: ...gh Performance HIPRO READ Control Bits Register Only bits 1 and 0 are valid BIt 1 BIt 0 0 1 HIPRO READ enabled 1 1 HIPRO READ ACR enabled Bit 0 is CSR enabled HIPRO READ enabled for every longword add...

Page 74: ...the SCRAMNet board software compatible with SCRAMNet interrupt addressing jump pins 2 and 4 Default setting connects pins 1 and 3 6 7 Media Card Connection J302 The Media Card is the interface between...

Page 75: ...e node is Inserted into the SCRAMNet Network ring This is the result of setting CSR 0 bit 15 6 11 2 Carrier Detect The green carrier detect LED is ON when there is a valid pair of transmit lights from...

Page 77: ...ol Register R W A 6 A 9 CSR8 General SCRAMNet Extended Control Register A 7 A 10 CSR9 SCRAMNet Interrupt on Error Mask A 8 A 11 CSR10 SCRAMNet Replicated Shared Memory Address LSW A 9 A 12 CSR11 SCRAM...

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Page 79: ...TT 3 Host Interrupt Enable HIE 4 Auxiliary Control RAM Enable ACRE 5 Interrupt on Memory Mask Match Enable IMME 6 Override RIE Flag ORF 7 Interrupt on Errors IOE 8 Network Interrupt Enable NIE 9 Overr...

Page 80: ...ll TXFAF 3 Always 0 Not Used 4 Interrupt FIFO Full IFF 5 Protocol Violation PV 6 Carrier Detect Failure CDF 7 Bad Message BB 8 Receiver Overflow RXO 9 Transmit Retry TXRTY 10 Transmit Retry Time out T...

Page 81: ...N 11 1024 vs 256 variable size max bytes LEN_LIMIT 12 Variable length messages on network VAR_LEN 13 HIPRO Write Enable HIPRO 14 Allow multiple native messages on network MULTIPLE_MSG 15 No Network Er...

Page 82: ...W REFERENCE A 4 CSR3 Number of Nodes and Node ID Bit Function Name 0 NN0 1 NN1 2 NN2 3 Node Number Count NN3 4 Valid After a Transmission from the Node NN4 5 NN5 6 NN6 7 NN7 8 NID0 9 NID1 10 NID2 11...

Page 83: ...A 5 VME3U H W REFERENCE A 5 CSR4 Interrupt Address LSW Bit Function Name 0 Always 0 1 Always 0 2 RFA2 3 RFA3 4 RFA4 5 RFA5 6 Interrupt FIFO Address Field LSW RFA6 7 RFA7 8 RFA8 9 RFA9 10 RFA10 11 RFA...

Page 84: ...F_E WRITE the Transmit Time out value to CSR5 and it will be stored in shadow memory A value of 0 will keep host provided data from leaving the Transmit FIFO A 7 CSR6 External Control Status Register...

Page 85: ...6 CLK line to MICROWIRE port CSR_CK 7 DIN line connected to the MICROWIRE DOUT pins E_DIN 8 Initiate initiation sequence CSR Reset CSR_RST 9 Override Counter mode GPC_FRE 10 Receive Interrupt Override...

Page 86: ...ask M_CD_FAIL 7 Bad Message mask M_BM 8 Receiver Overflow mask M_RX_OVR 9 Transmitter Retry mask M_RETRY 10 Transmitter Retry Time out M_RETRY_T_O 11 Redundant Transmit Receive Fault mask M_FAULT 12 I...

Page 87: ...LSW Bit Function Name 0 Enable comparator for SM access SMA_ENABLE 11 1 Reserved 0 12 SMA12 13 Shared Memory Address SMA13 14 SMA14 15 SMA15 A 12 CSR11 SCRAMNet Shared Memory Address MSW Bit Function...

Page 88: ...ging Register Refer to Section 4 paragraph 4 2 1 and Section 5 page 5 15 for additional information Bit Function Name 0 Enables Virtual Paging when set VP 4 1 Always 0 0 5 VP_A12 6 VP_A13 7 VP_A14 8 V...

Page 89: ...NT 9 10 Counter Timer register RD_COUNT 10 11 Counter Timer register RD_COUNT 11 12 Counter Timer register RD_COUNT 12 13 Counter Timer register RD_COUNT 13 14 Counter Timer register RD_COUNT 14 15 Co...

Page 90: ...2 VME3U H W REFERENCE A 18 Auxiliary Control RAM R W Bit Function Name 0 Receive Interrupt Enable RIE 1 Transmit Interrupt Enable TIE 2 External Trigger 1 Host Read Write ET1 3 External Trigger 2 Netw...

Page 91: ...B APPENDIX B CABLE KIT TABLE OF CONTENTS B 1 Introduction B 1 B 2 Cable Connections B 1 B 2 1 Cabinet Kit Connections B 2...

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Page 93: ...ths vary depending upon the distance between the installed board s media card and the cabinet kit Connect cables between the SCRAMNet Network board media card receiver Rx1 and Rx2 and the bulkhead pla...

Page 95: ...C APPENDIX C SPECIFICATIONS TABLE OF CONTENTS C 1 Hardware Specifications C 1 C 2 Bus Voltage Specifications C 2 C 3 Part Number C 2 C 4 Board Dimensions C 3 C 5 Fiber Optic Bypass Switch C 4...

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Page 97: ...sing Network Line Transmission Rate 150 million bits second Message Length Fixed Length 82 Bits Variable Length 256 or 1024 Data Bytes Maximum Maximum Nodes on Network Ring 256 Error Correction Availa...

Page 98: ...25 V 0 125 V 50 Mv GND Ground Reference Not used by SCRAMNet VME3U C 3 Part Number The VME3U adapter part number is in the form H AS D3VMEL2M 00 where CODE DEFINITION H Hardware AS Top Level Assembly...

Page 103: ...terface Logic to Shared Memory CSR D 2 D 3 1 ASIC Internal CSR READ D 2 D 3 2 ASIC Internal CSR WRITE D 3 D 4 Host Interface Logic to Host Specific CSR D 4 D 4 1 Host Specific CSR READ D 4 D 5 Access...

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Page 105: ...al Port RAM Controller Access Types Access Type Port Cycle Time Host WRITE 1 240 ns Host READ 1 133 ns Network WRITE 2 133 ns D 2 1 Contention The SCRAMNet Network being an intelligent peripheral does...

Page 106: ...SIC RESOURCES HOST SPECIFIC RESOURCES HREQ Figure D 1 ASIC Resources This format is typically a READ or WRITE operation to the ASIC resources the shared memory and CSRs D 3 1 ASIC Internal CSR READ Th...

Page 107: ...D 2 READ From Internal CSR D 3 2 ASIC Internal CSR WRITE This is a typical WRITE cycle of an ASIC internal CSR AS and DS fall HREQ requested for a particular CSR address Data accepted and ASIC assert...

Page 108: ...D 4 1 Host Specific CSR READ All READ operations on the external CSRs do not go through normal ASIC data paths Therefore timings for this cycle varies from other CSR READ cycles These external CSRs a...

Page 109: ...shown in This table does not include host timing The worst case scenerio resulting in maximum access times would be a host WRITE followed immediately by another host WRITE and simultaneous receipt of...

Page 110: ...n Figure D 6 is a functional diagram of the worst case scenerio B U S HOST LOGIC N E T W O R K HW NW DTACK HACK ASIC NW NW DUAL PORT RAM CONTROLLER MEMORY H W Figure D 6 Two Host WRITEs in Contention...

Page 111: ...WRITE if the worst case scenario continues i e HW1 NW1 NW2 NW3 HW2 NW4 NW5 HW3 NW6 NW7 HW4 The maximum time for a host READ or WRITE would occur with host back to back HREQs within 30 ns combined with...

Page 112: ...ycle 0 ns per VME Spec 399 ns Figure D 7 Back to Back Host READs Figure D 8 illustrates how the DPRC must manage two inputs The network WRITEs have the higher priority Consequently in this worst case...

Page 113: ...terface logic waits for the first Data Strobe to fall and then delays 106 ns to allow address decode and attain bus stability In the first VME cycle the host logic raises a host WRITE request to the D...

Page 114: ...ted since the first one is still being serviced Additionally in this worst case scenerio three network transactions must be processed before the previous host request is cleared Once the network trans...

Page 115: ...E APPENDIX E CONFIGURATION AIDS TABLE OF CONTENTS...

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Page 117: ...t vector data intrpt vector data intrpt vector data intrpt vector reserved reserved reserved reserved reserved reserved reserved reserved ACR LED STATUS 0 1 2 3 RIE TIE EXT TRG 1 EXT TRG 2 4 5 6 7 HIP...

Page 118: ...ed reserved reserved CSR 9 CSR 11 CSR 13 CSR 15 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 TX FIFO FULL MASK TX FIFO NOT EMP MASK TX FIFO 7 8 FULL MASK BIST STREAM R O RX FIFO FULL MASK PROTOCOL VIOL MASK...

Page 119: ...FIGURATION AID Copyright 1995 SYSIRAN Corp E 3 VME3U H W REFERENCE SCRAMNet NETWORK CONFIGURATION DATA SHEET NODE ID HOST MACHINE MEMORY ADDRESS BUS MEMORY SIZE CSR ADDRESS BUS INT LEVEL SCRAMNet SERI...

Page 121: ...F APPENDIX F ACRONYMS...

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Page 123: ...B Kilobyte 1024 bytes LAN Local Area Network LSFR Linear Feedback Shift Register Longword 32 bit or 4 byte word LSB Least Significant Byte or Bit LSHLW Least Significant Half of a Longword LSP Least S...

Page 125: ...G APPENDIX G GLOSSARY...

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Page 127: ...ses the arbiter to sample the bus requests again backplane A printed circuit board pcb with 96 pin connectors and signal paths that bus the connector pins Some systems have a single pcb called the J1...

Page 128: ...size may be set to either 256 bytes or 1024 bytes bus timer A functional module that measures the time each data transfer takes on the DTB and terminates the DTB cycle if a transfer takes too long Wit...

Page 129: ...ntrast with programmed I O PIO transfer device interrupt An interrupt received on interrupt priority levels 20 23 Device interrupts can be requested only by devices controllers and memories DTB A mnem...

Page 130: ...an access occurs to one of these assigned locations the location monitor generates an on board signal locking a page in memory Making a page ineligible for either paging or swapping A page stays locke...

Page 131: ...s when the master broadcasts an address and an address modifier Each slave captures this address and address modifier and checks to see if it is to respond to the cycle If so it retrieves the data fro...

Page 132: ...se cycles specify its participation transfers data between itself and the master slot A position where a board can be inserted into a backplane If the system has both a J1 and a J2 backplane or a comb...

Page 133: ...ers and intelligent peripheral devices can be connected The term VME stands for Versa Module Eurocard This non proprietary bus conforms to the American National IEEE Standard 1014 ANSI IEEE std 1014 w...

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