IPC/RSL8xxx-XxxxE: user documentation
DOC/IPC_RSL8-E; V1.9
© Syslogic Datentechnik AG, Switzerland, http://www.syslogic.com
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3.3.2.
LVDS Display-Interface (optional)
The LVDS display interface is an optional interface for direct connection of an external TFT
display. It supports 3.3V 8-bit Single and Dual Link LVDS TFT panels on connector P32.
Direct inverter connection is provided through P31 if power requirement is not to high.
Note that special BIOS-Settings are required for operation of the LVDS display interface.
Contact Syslogic technical support for details.
Device Connection (LVDS-Panel)
Mating connector type: Hirose DF13-40DS-1.25C, Crimp contact DF13-3032SCF.
Pin
Number
Signal
Pin
Number
Remarks
1
VCC_LCD (3.3Vdc)
2
VCC_LCD (3.3Vdc)
3
GND
4
GND
5
LVDS_A0-
6
7
GND
8
LVDS_A1-
9
10
GND
11
LVDS_A2-
12
13
GND
14
LVDS_ACLK0-
15
LVD
16
GND
17
LVDS_A3-
18
19
FPMODE (Switch S5 bit 2)
Mode control (off=1k pullup to 3.3V /
on=ground)
20
FPHMODE (Switch S5 bit 3)
Mode control (off=1k pullup to 3.3V /
on=ground)
21
GND
22
GND
23
LVDS_B0-
24
25
GND
26
LVDS_B1-
27
28
GND
29
LVDS_B2-
30
31
GND
32
LVDS_BCLK0-
33
LVD
34
GND
35
LVDS_B3-
36
37
GND
38
VCC_LCD5 (5Vdc)
39
VCC_LCD5 (5Vdc)
40
VCC_LCD5 (5Vdc)
Tab. 9 LVDS connector P32 (Hirose DF13A-40DP-1.25V)
Important Note
Do not draw more than 1.0 Ampere from VCC_LCD (max. 0.5 Ampere per pin).
This interface is intended for case internal use only.