IPC/RSL8xxx-XxxxE: user documentation
DOC/IPC_RSL8-E; V1.9
© Syslogic Datentechnik AG, Switzerland, http://www.syslogic.com
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4.3.7.
Temperature Sensor
The Temperature Sensor is built up using an LM75 compatible temperature sensor
programmable through an I2C interface. The I2C interface programming is done through the
I2C Register of the RSL8. For detailed programming information please refer to the National
Semiconductor LM75 datasheet or similar documentation.
Poweron default setting for OVERTMP* is 80°C chip temperature.
4.3.8.
Watchdog
The watchdog is disabled by default on poweron and must be enabled by the application
program.
Before enabling the watchdog by setting the WDEN bit in the SL8 Setup Register, the
watchdog action (RESET or NMI) must be programmed in the SL8 Control Register (bit
WDNMI) and the timeout value must be configured using switch S1 and/or the SL8 Watchdog
Configuration Register.
If RESET activation is selected, the watchdog generates a hardware reset if it is not triggered
within the configured timeout window by writing the WDTRIG bit in the RSL8 Control
Register. The application must check the WDG* bit in the RSL8 Status Register uppon startup
to identify the Watchdog as the source of the reset, and it must issue a hardware reset (by
writing the value 0a5h to the RSL8 Option ID Register) to clear the WDG* flag. Otherwise the
system resets again as soon as the Watchdog is started.
If NMI activation is selected, the watchdog generates a Non Maskable Interrupt to the
processor if it is not triggered within the configured timeout window by writing the WDTRIG
bit in the RSL8 Control Register. Note that enabling the NMI input of the processor also
requires setting bit 7 of I/O port 70h (NMI mask) and clearing bit 3 of I/O port 61h (Port B
IOCHK# enable). The NMI routine must check the WDG* bit in the RSL8 Status Register to
identify the watchdog as the source of the NMI, and it must issue a hardware reset (by writing
the value 0a5h to the RSL8 Option ID Register) to clear the WDG* flag. Otherwise the NMI
routine is entered again as soon as the watchdog is started.
Sample code showing the initialization and triggering of the watchdog is available for RESET
and NMI mode in the free IPC/IOCOMSW-1A package.
Note
The NMI mask bit (bit 7 of I/O port 70h) is write only. Typically it is enabled by the
BIOS and should not be disabled by application software.
4.3.9.
PC/104 Bus Interface
For detailed description of PC/104 add-on board programming please consult PC/104 and ISA
bus standard documentation and related PC/AT architecture literature as well as the add-on
boards documentation.
