Supero Super P6DNF, User Manual

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SUPER P6DNF/P6SNF User's Manual
CPU to IDE Posting
Set this option to Enabled to enable posted messages from the
CPU to the IDE controller. The settings are: Disabled or Enabled.
The Optimal and Fail-Safe default settings are Enabled.
USWC Write Posting
This option is for USWC Write Posting to PMC register 53h, bit 5.
The settings are: Disabled or Enabled. The Optimal and Fail-Safe
default settings are Enabled.
CPU to PCI Posting
Set this option to Enabled to enable posted messages from the
CPU to the PCI bus. The settings are: Disabled or Enabled. The
Optimal and Fail-Safe default settings are Enabled.
PCI to DRAM Pipeline
Set this option to Enabled to allow the PCI bridge to run back-to-
back cycle to access the DRAM. The settings are: Disabled or En-
abled. The Optimal and Fail-Safe default settings are Enabled.
PCI Burst Write Combine
When Enabled, PCI bridge can combine memory writes to succes-
sive doublewords into a single memory write transaction using lin-
ear addressing. The combined doublewords must be written in the
same order in which they were posted. The settings are: Disabled
or Enabled. The Optimal and Fail-Safe default settings are En-
abled.