4.6 Status Model
4 – 61
in the LDCR causes the bit to be set in the LDEV. Likewise, if a bit is
set in LDNT, then a 1
→
0 transition in the LDCR causes the bit to be
set in the LDEV.
All combinations of LDPT and LDNT settings are valid. At power-
on, both LDPT and LDNT are cleared.
4.6.4.2 Laser diode event (LDEV)
This 16-bit wide register monitors selected events in the LDCR, based
on transitions selected in LDPT and LDNT. When the selected transi-
tion(s) occur, the corresponding bit is set. Reading the register clear
it (reading a single bit clears only that bit). This register is cleared by
the
*CLS
command.
In addition to monitored events from the LDCR, several discrete
events are directly defined in LDEV without corresponding real-time
condition bits in the LDCR. These are:
Weight
Bit
Flag
1024
10
VTRIP
2048
11
OPEN
4096
12
TEC OFF
8192
13
TMAX
16384
14
TMIN
32768
15
TFAULT
VTRIP : Indicates the LD tripped o
ff
due to overvoltage.
OPEN : Indicates the LD tripped due to open circuit.
TEC OFF : Indicates LD tripped o
ff
due to the TEC being o
ff
(see
ATOF
).
TMAX : Indicates the LD tripped o
ff
due to
T
max
being exceeded.
TMIN : Indicates the LD tripped o
ff
due to
T
min
being exceeded.
TFAULT : Indicates the LD tripped o
ff
due to a temperature sensor fault.
4.6.4.3 Laser diode status enable (LDSE)
This is a 16-bit wide register that masks the LDEV register. The
logical OR of the bitwise AND of LDEV and LDEN produces the
LDSB message in the Status Byte register (SB).
4.6.5
TEC controller condition (TECR)
The Laser Diode Condition Register consists of 10 condition flags
that reflect the real-time condition of the TEC portion of the LDC500.
Reading the
TECR
has no e
ff
ect on any values.
LDC500 Series Laser Diode Controllers
