Sony BVP-570, Maintenance Manual

Page: 714 / 806

7-22
BVP-570
IC
STK10C68-S35 (SIMTEK)FLAT PACKAGE SN74HCT244APW-E05 (TI)FLAT PACKAGE
TC74VHC244FT(EL) (TOSHIBA)FLAT PACKAGE
G
0
0
x
A
0
1
x
Y
0
1
HI-Z
0
1
x
HI-Z
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
: HIGH IMPEDANCE
16 17 18 19 20
G2
G1
G1
15
V
DD
GND
14 13 12 11
A Y = Y A
G G
7 6 5 4 3 2 1
2
4
6
8
11
13
15
17
8 9 10
18
16
14
12
9
7
5
3
1 19
G2
G
OR
2
4
6
8
18
16
14
12
1
11
13
15
17
9
7
5
3
19
G
C-MOS BUS BUFFER WITH 3-STATE OUTPUTS
—TOP VIEW—
TC4W53FU (TOSHIBA)CHIP PACKAGE
TC4W53FU(TE12R)
1
INH
0
0
1
A
0
1
x
ch0
ch1
OPEN
2
3
OPEN
INH V
EE
ch1
ch0
2 3
C
A
6
7
1
5
GND 4
8 V
DD
6
7
5
ON
CHANNEL
CONT. INPUT
C-MOS 2-CHANNEL MULTIPLEXER/DEMULTIPLEXER
—TOP VIEW—
0
1
x
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
ROW
DECODER
STATIC RAM
ARRAY
256 x 256
EEPROM ARRAY
256 x 256
COLUMN
DECODER
COLUMN
I/O
A3
7
A4
6
A5
5
A6
4
A7
3
A8
25
A9
24
A12
2
STORE
RECALL
A0
10
A1
9
A2
8
A10
21
A11
23
OE
22
WE
27
NE
1
CE
20
8
8 8
8
8
D0
11
D1
12
D2
13
D3
15
D4
16
D5
17
D6
18
D7
19
INPUT
BUFFER
STORE/RECALL
CONTROL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
NE
IN
A12
IN
A7
IN
A6
IN
A5
IN
A4
IN
A3
IN
A2
IN
A1
IN
A0
IN
D0
IN/OUT
D1
IN/OUT
D2
IN/OUT
WE
IN
A8
IN
A9
IN
A11
IN
OE
IN
A10
IN
CE
IN
D7
IN/OUT
D6
IN/OUT
D5
IN/OUT
D4
IN/OUT
D3
IN/OUT
11
12
13
15
16
17
18
19
D0
D1
D2
D3
D4
D5
D6
D7
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
A11
A12
10
9
8
7
6
5
4
3
25
24
21
23
2
INPUT
A0 - A12
CE
NE
OE
WE
INPUT/OUTPUT
D0 - D7
: ADDRESS
: CHIP ENABLE
: NONVOLATILE ENABLE
: OUTPUT ENABLE
: WRITE ENABLE
: DATA
V
DD
NC
GND
1
NE
27
WE
22
OE
20
CE
C-MOS 8 K x 8-BIT NONVOLATILE SRAM
—TOP VIEW—
TC4S69F (TOSHIBA)CHIP PACKAGE
TC4S69F(TE85R)
TC7S04FU(TE85R) (TOSHIBA)FLAT PACKAGE
TC7SH04FU (TOSHIBA)CHIP PACKAGE
TC7SH04FU-TE85R
TC4W66FU(TE12R) (TOSHIBA)FLAT PACKAGE
TC74AC86F (TOSHIBA)FLAT PACKAGE
GND
V
DD
1 2 3 4 5 6 7
8
0
1 : LOW LEVEL
: HIGH LEVEL
A
B
Y
A
0
0
1
1
Y
0
1
1
0
B
0
1
0
1
Y =
A
• B
+
A •
B
14 13 12 11 10 9
C-MOS QUAD EXCLUSIVE OR GATES
—TOP VIEW—
1
1
0
1
OFF
ON
2
IN/OUT
CONTROL
IN/OUT
3
8 V
DD
0 : LOW LEVEL
1 : HIGH LEVEL
6
7
2
7
5 6
3
5
SWITCH CONTROL
GND 4
C-MOS DUAL BILATERAL SWITCH
—TOP VIEW—
1
2
GND 3
5 V
DD
4
A A
Y =
2 4
Y
A
0
1
Y
1
0
0 : LOW LEVEL
1 : HIGH LEVEL
Y =
A
C-MOS INVERTER
—TOP VIEW—