Sony BVP-570, Maintenance Manual

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7-21
BVP-570
IC
PCF8574T-T (PHILIPS)
INTERRUPT
LOGIC
INPUT
FILTER
POWER-ON
RESET
LP FILTER
SHIFT
REGISTER
I/O
PORTS
8 BIT
INT
13
A0
1
A1
2
A2
3
SCL
14
SDA
15
V DD
16
V SS
8
PCF8574
PCF8574A
P0
4
P1
5
P2
6
P3
7
P4
9
P5
10
P6
11
P7
12
write pulse
read pulse
I 2 C BUS
CONTROL
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
A0
IN
A1
IN
A2
IN
P0
I/O
P1
I/O
P2
I/O
P3
I/O
SDA
SCL
INT
P7
I/O
P6
I/O
P5
I/O
P4
I/O
13
4
5
6
7
9
10
11
12
15
INT
P0
P1
P2
P3
P4
P5
P6
P7
SDA
A0
A1
A2
SCL
1
2
3
14
INPUT
A0 - A2
SCL
OUTPUT
INT
SDA
INPUT/OUTPUT
P0 - P7
: ADDRESS INPUTS
: SYSTEM CLOCK LINE
: INTERRUPT OUTPUT
: SERIAL DATA LINE
: 8-BITS QUASI-BIDIRECTIONAL I/O PORT
GND
V
DD
C-MOS REMOTE 8-BIT I/O EXPANDER
—TOP VIEW—
RTC-4553B (EPSON)
WR
IN
S
IN
SCK
IN
L1
IN
L2
IN
L3
IN
1
2
3
4
5
6
7
14
13
12
11
10
9
8
TP
OUT
S
OUT
CS1
IN
CS0
IN
L5
IN
L4
IN
GND
V
DD
4
3
11
12
2
5
6
7
9
10
SCK
SIN
CS0
CS1
WR
L1
L2
L3
L4
L5
S OUT
TP OUT
13
14
INPUT
CS0
CS1
L1 - L5
SCK
SIN
WR
OUTPUT
SOUT
TPOUT
: CHIP SELECT (L : ACCESS ENABLE, H : SOUT HIGH Z)
: POWER DOWN DETECTION
: TEST IN
: SERIAL SYNC SIGNAL
: SERIAL ADDRESS/DATA
: WRITING SELECT (L : WRITING, H : READING)
: SERIAL ADDRESS/DATA
: REFERENCE SIGNAL
OSC DIVIDING OUTPUT CONTROL
14
TP OUT
4
SCK
3
SIN
12
CS1
11
CS0
2
WR
CONTROL
CONTROL
SECOND
SHIFT
REGISTER
OUTPUT
CONTROL
TEST
5 - 7, 9, 10
L1 - L3
L4, L5
MINUTE HOUR DAY DATE MONTH YEAR
RAM
(120-BIT)
CONTROL
REGISTER
(3)
CONTROL
REGISTER
(2)
CONTROL
REGISTER
(1)
13
S OUT
C-MOS REAL TIME CLOCK
—TOP VIEW—
SN74HC08ANS (TI)FLAT PACKAGE
SN74HC08ANS-E05
SN74HC08APW-E05 (TI)FLAT PACKAGE
SN74HCT08APW-E05
SN74HCT08APW-E20 (TI)FLAT PACKAGE
TC74VHC08FT(EL) (TOSHIBA)FLAT PACKAGE
1 2 3 4 5 6 7
14 13 12 11 10 9 8
GND
V DD
A
0
0
1
1
B
0
1
0
1
Y
0
0
0
1
0
1
: LOW LEVEL
: HIGH LEVEL
A
B
A
B
Y Y =
Y = A • B =
A
+
B
C-MOS QUAD 2-INPUT AND GATES
—TOP VIEW—
SN74HC574APW-E05
SN74HC574APW-E20 (TI)
1
2
3
4
5
6
7
8
9
10
EN
IN
D1
IN
D2
IN
D3
IN
D4
IN
D5
IN
D6
IN
D7
IN
D8
IN
20
19
18
17
16
15
14
13
12
11 GND
V
DD
Q1
OUT
Q2
OUT
Q3
OUT
Q4
OUT
Q5
OUT
Q6
OUT
Q7
OUT
Q8
OUT
CK
IN
2
3
4
5
6
7
8
9
11
D1
D2
D3
D4
D5
D6
D7
D8
Q1
Q2
Q3
Q4
Q5
Q6
Q7
Q8
19
18
17
16
15
14
13
12
EN
1
EN
0
0
0
1
CK
x
D
1
0
x
x
INPUTS OUT
Q
1
0
Q
0
HI-Z
EACH FLIP-FLOP
D Q
Q
EN EN
Q
Q D
11
1
CK
EN
2 19 3 18 4 17 5 16 6 15 7 14 8 13 9 12
D1 Q1 D2 Q2 D3 Q3 D4 Q4 D5 Q5 D6 Q6 D7 Q7 D8 Q8
C-MOS 3-STATE D-TYPE EDGE-TRIGGERED FLIP-FLOP
—TOP VIEW—
0
1
x
HI-Z
Q
0
: LOW LEVEL
: HIGH LEVEL
: DON’T CARE
: HIGH IMPEDANCE
: NONSTABLE