SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 135
Version 1.7
Internal High RC Oscillator Frequency
( Vdd = 2.4V ~ 3.6V, Temperature: 0
℃
~ 50
℃
)
8-2.5%
8
8+2.5%
Note: Analog Parts including Regulator, PGIA and ADC.
(All of voltages refer to Vdd=3V F
OSC
= IHRC (8MHz), ambient temperature is 25
C unless otherwise note.)
PARAMETER
SYM.
DESCRIPTION
MIN.
TYP.
MAX.
UNIT
Analog to Digital Converter
Operating current
I
DD_ADC
Run mode @ 2.4V
-
160
250
uA
Power down current
I
PDN
Stop mode @ 2.4V
-
0.1
-
μA
Conversion rate
(Word Rare, WR)
F
WR
ADC Clock=250KHz, OSR=32768
-
7.6
-
Sps
ADC Clock=250KHz, OSR=64
-
3.9
-
kSps
Reference Voltage Input
absolutely Voltage
V
AIN
ADC Internal Vref
0.4
-
1.4
V
Reference Voltage Range
Vref
ADC Reference voltage range
0.36
-
0.96
V
Integral non-linearity
INL
PGIAx128, ADC Input Range ±0.9xVref
-
0.01
-
%FSR
No missing code
NMC
ADC range
±
0.9 x Vref
20
-
-
bit
ADC Noise free bits
NFB
Gain:1, Vref:0.8V, OSR:32768, Input-short
-
18.4
-
bit
Gain:128, Vref:0.8V, OSR:32768, Input-short
-
15.9
-
bit
Effective number of bits
ENOB
Gain=128, Vref=0.8V, OSR=32768, Input-short
-
18.6
-
bit
Gain=1, Vref=0.8V, OSR:32768, Input-short
-
21.1
-
bit
ADC Input range
V
AIN
ADC input signal, signal after PGIA application
0.4
-
1.4
V
Temperature sensor inaccuracy
E
TS
Inaccuracy range vs. real Temp.
-
±
10
-
%
PGIA
PGIA Current consumption
I
DD_PGIA
Run mode @ 2.4V
-
150
-
uA
Power down current
I
PDN
Stop mode @ 2.4V
-
0.1
-
uA
Input offset voltage
Vos
-
25
-
uV
Bandwidth
BW
-
-
5
kHz
PGIA Gain Range
Gain
VDD = 2.4V, PGIA x 128
110
128
150
Gain
PGIA Input Range
Vopin
AI+, AI- signal input range. (AVDDR = 2.4V)
0.4
-
1.4
V
PGIA Output Range
Vopout
Signal output range. (AVDDR = 2.4V)
0.4
-
1.4
V
Band gap Reference
Band gap Reference Voltage
V
BG
VDD: 2.4V ~ 3.6V
1.18
1.23
1.28
V
Operating current
I
BG
Run mode @ 2.4V
-
120
-
uA
Regulator
Regulator output voltage AVDDR
V
AVDDR
AVDDR set as 2.4V
2.25
2.4
2.55
V
Regulator output current capacity
I
VA+
AVDDR,AVE output current ability
-
5
10
mA
Quiescent current
I
QI
AVDDR +AVE
-
120
-
uA
Regulator output voltage AVE+
V
AVE+
AVE+ set as 2.0V
1.85
2.0
2.15
V
V
AVE
sinking capacity
I
SNK
Sink Current Capacity @ AVE set 1V or 0.75V
-
-
1
mA
LCD Driver
R-Type LCD Operation Current
I
RLCD
VDD:3V, 1/3 bias, No panel, R-LCD
(VAR[1:0]=00)
30
-
uA
(VDD:3V, 1/3 bias, No panel, R-LCD
(VAR[1:0]=01)
8
-
VDD:3V, 1/3 bias, No panel, R-LCD
(VAR[1:0]=10)
4
-
VDD:3V, 1/3 bias, No panel, R-LCD
(VAR[1:0]=11)
2
-
C-Type LCD Operation Current
I
CLCD
1/3 bias, LCD Charge pump + Bandgap current
80
uA
C-Type VLCD output Voltage
V
LCD
VLCD set 3V,
2.8
3.0
3.2
V
VLCD Variation vs. VDD and Temp
VDD: 2.4~3.6V. Temp.: -10 ~ 50
℃
-30
-
30
mV
LBT Driver
Internal Low-Battery detect voltage
V
ILBT
Condition: V
LBT
=3.6V
3.4
3.6
3.8
V
Condition: V
LBT
=3.0V
2.8
3.0
3.2
Condition: V
LBT
=2.4V
2.25
2.4
2.55
External Low-Battery detect voltage
V
ELBT
Condition: VDD =2.2~3.6V, P10 input comparator
1.1
1.2
1.3
