SONIX SN8P2977, User Manual

Page: 112 / 146

SN8P2977
8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC
SONiX TECHNOLOGY CO., LTD
Page 112
Version 1.7
13.6.3
ADC Gain and Offset
The ADC builds in internal Gain Option with selective range of x1 and x2 for additional signal amplification expect PGIA.
The ADC Gain setting is controlled by
ADGN [2:0] bits in register ADCM1 . The analog signal after ADC Gain
amplification, it can be adjusted offset level by subtraction or addition function, to increase the signal operation range of
ADC in weigh-scales application. ADC Offset function is controlled by
OFSEL [1:0] bits in register ADMC2.
The following shows ADC output code calculation (differential mode):
16bits:
   
 
-32768 ~ 32767 2
_
) 1 16 (
  
     

Vref
V Gain ADC PGIA AI AI
Offset
18bits :
   
 
-131072 ~ 131071 2
_
) 1 18 (
  
     

Vref
V Gain ADC PGIA AI AI
Offset
20bits :
     
-524288 ~ 524287 2
_
) 1 20 (
  
     

Vref
V Gain ADC PGIA AI AI
Offset
V
offset
: 0, -1/4, -1/2 or -3/4 x Vref
PGIA: 1x ~ 200x
ADC_Gain : 1x and 2x
Vref Source: Internal Vref
Vref Range: 0.225V ~ 1.6V