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SN8P2977

8-Bit Micro-Controller with Regulator, PGIA, 24-bit ADC

SONiX TECHNOLOGY CO., LTD

Page 105

Version 1.7

13.3 Voltage Regulator

SN8P2977 is built in voltage regulators, which can provide a stable 2.4V/2.8V/3.2V (pin AVDDR) and

0.75V/1.0V1.5V/2.0V (pin AVE+) with maximum 10mA current driving capacity. Register VREG can enable or disable
AVDDR and AVE output voltage. Because the power of PGIA and ADC are came from AVDDR, turn on AVDDR
(AVDDRENB = 1) first before enabling PGIA and ADC. The AVDDR voltage was regulated from VDD.

13.3.1

Voltage Regulator Control Register

090H

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

VREG

BGRENB

-

AVENB

AVESEL1

AVESEL0 AVDDRENB AVDDRSEL1 AVDDRSEL0

R/W

R/W

-

R/W

R/W

R/W

R/W

R/W

R/W

After Reset

0

-

0

1

0

0

0

1

Bit7:

BGRENB:

Band Gap Reference voltage enable control bit

0 = Disable Band Gap Reference Voltage
1 = Enable Band Gap Reference Voltage

Bit5:

AVENB:

Regulator (AVE) voltage Enable control bit.

0 = Disable Regulator and AVE Output voltage.
1 = Enable Regulator and AVE Output voltage.

Note:

※

When AVE enable & AVE set 1.5V/2.0V, AVE pin have to connect 1uf capacitors to ground.

Bit[4:3]:

AVESEL[1:0]:

Regulator (AVE) voltage output voltage control bit.

00 = AVE 0.75V. (Sink only)

01 = AVE 1.0V. (Sink only)

10 = AVE 1.5V. (Drive only)

11 = AVE 2.0V. (Drive only)

Bit2:

AVDDRENB:

Regulator (AVDDR) voltage Enable control bit.

0 = Disable Regulator and AVDDR Output voltage.
1 = Enable Regulator and AVDDR Output voltage.

Bit[1:0]:

AVDDRSEL[1:0]:

Regulator (AVDDR) voltage output voltage control bit.

00 = Reserved.

01 = AVDDR 2.4V.

10 = AVDDR 2.8V.

11 = AVDDR 3.2V.



Note_1: Band Gap Reference voltage must be enable (FBRGEN), before following function accessing:

(Reference AMPM1 and AMPM2 register for detail information)

(1)Regulators of AVDDR.
(2)PGIA Function.
(3)ADC Function.
(4)Low Battery Detection Function.



Note_2: All current consumptions from AVE+.(ex. Load cell or AVDDR will NOT double.)



Note_3: PGIA can work in Normal, Slow or Green Mode, when high clock is still running (STPHX=0).



Note_4: Add 10ms delay time after enabling each regulators, AVDDR/AVE to avoid VDD drop in CR2032

battery application.

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Summary of Contents for SN8P2977

Page 1: ...uthorized for us as components in systems intended for surgical implant into the body or other applications intended to support or sustain life or for any other application in which the failure of the...

Page 2: ...ion 15 Modify 13 6 7 ADC Data Register Note description 16 Modify 14 APPLICATION CIRCUIT 17 Modify 17 ELECTRICAL CHARACTERISTIC Ver1 3 2017 02 1 Modify 13 4 1CHS Analog input signal channel selection...

Page 3: ...MEMORY RAM 27 2 1 5 SYSTEM REGISTER 28 2 1 6 ACCUMULATOR 31 2 1 7 PROGRAM FLAG 32 2 1 8 PROGRAM COUNTER 33 2 1 9 MULTI ADDRESS JUMPING 35 2 1 10 Y Z REGISTERS 36 2 1 11 H L REGISTERS 37 2 1 12 R REGIS...

Page 4: ...ROUTINE 58 6 6 EXTERNAL INTERRUPT OPERATION 59 6 7 MULTI INTERRUPT OPERATION 60 7 7 7 I O PORT 62 7 1 I O PORT MODE 62 7 2 I O PIN SHARE WITH LCD FUNCTION 62 7 3 I O PULL UP REGISTER 64 7 4 I O PORT D...

Page 5: ...LCD DRIVER 94 11 1 OVERVIEW 94 11 2 LCD TIMING 94 11 3 LCDM1 REGISTER 96 11 4 LCDM2 REGISTER 96 11 5 C TYPE LCD DRIVER MODE 98 11 6 R TYPE LCD DRIVER MODE 99 11 7 LCD RAM LOCATION 101 1 1 12 2 2 IN S...

Page 6: ...1 1 ICE IN CIRCUIT EMULATION 128 16 1 2 OTP WRITER 128 16 1 3 IDE INTEGRATED DEVELOPMENT ENVIRONMENT 128 16 2 OTP PROGRAMMING PIN TO TRANSITION BOARD MAPPING 129 16 3 APPENDIX A EV KIT BOARD CIRCUIT...

Page 7: ...SN8P2977 8 Bit Micro Controller with Regulator PGIA 24 bit ADC SONiX TECHNOLOGY CO LTD Page 7 V1 7 19 3 MARKING EXAMPLE 145 19 4 DATECODE SYSTEM 145...

Page 8: ...V 2 8V 3 2V 2 4V 2 8V 3 2V Load cell Power AVDDR AVDDR or AVE ADC Input Channel 1 fully differential Input 2 fully differential Input 4 single ended Input ADC Reference External Voltage V R R No Yes A...

Page 9: ...only One Temperature Sensor Maximum instruction cycle is 2 LCD driver JMP instruction jumps to all ROM area 1 3 or 1 2 bias voltage All ROM area look up table function MOVC 4 common 16 segment Fcpu I...

Page 10: ...TOR RAM SYSTEM REGISTERS LVD WATCHDOG TIMER TIMER COUNTER ALU PC FLAGS IR OTP ROM AVDDR AVE Internal High RC oscillator P0 P1 Internal Low RC oscillator Regulator PGIA Low Battery Comparator Internal...

Page 11: ...4 45 P25 SEG10 SEG2 P35 5 44 P24 SEG11 SEG1 P36 6 43 P23 SEG12 SEG0 P37 7 42 P22 SEG13 COM3 8 41 P21 SEG14 COM2 9 40 P20 SEG15 COM1 10 39 NC COM0 11 38 NC VLCD VPP 12 37 DVDD NC 13 36 DVSS NC 14 35 P...

Page 12: ...SEG11 P24 SEG12 P23 SEG13 P22 48 47 46 45 44 43 42 41 40 39 38 37 P36 SEG1 1 O 36 SEG14 P21 P37 SEG0 2 35 SEG15 P20 COM3 3 34 NC COM2 4 33 NC COM1 5 32 DVDD COM0 6 SN8P2977 31 DVSS VLCD VPP 7 30 P07...

Page 13: ...VSS 9 20 P30 SEG7 INT1 P01 10 19 P27 SEG8 P02 11 18 P26 SEG9 Buzzer P03 12 17 P25 SEG10 TX P04 13 16 P24 SEG11 P22 SEG13 14 15 P23 SEG12 VLCD VPP AVDDR AI1 AI2 VSS VDD INT1 P0 1 P0 2 1 2 3 4 5 6 7 8 P...

Page 14: ...P02 7 14 P21 SEG14 Buzzer P03 8 13 P20 SEG15 TX P04 9 12 DVDD RX P05 10 11 DVSS SN8P2972 SOP18 VLCD VPP 1 18 DVDD AVDDR 2 17 DVSS AVSS 3 16 P07 LXOUT AVDD 4 15 P06 LXIN AI1 5 14 P05 RX AI2 6 13 P04 T...

Page 15: ...with LCD SEG4 P32 SEG5 I O P32 IO function share with LCD SEG5 P31 SEG6 I O P31 IO function share with LCD SEG6 P30 SEG7 I O P30 IO function share with LCD SEG7 P27 SEG8 I O P27 IO function share wit...

Page 16: ...t ADC SONiX TECHNOLOGY CO LTD Page 16 V1 7 1 7 PIN CIRCUIT DIAGRAMS Port 0 Port 1 structure Port 2 Port 3 structure Pull Up Pin Output Latch PnM PnUR Input Bus PnM Output Bus PnSEG LCD SEG Function Pu...

Page 17: ...EMORY ROM 4K words ROM ROM 0000H Reset vector User reset vector 0001H General purpose area Jump to user start address 0002H Jump to user start address 0003H Jump to user start address 0004H Reserved 0...

Page 18: ...set After power on reset or watchdog timer overflow reset then the chip will restart the program from address 0000h and all system registers will be set as default values The following example shows t...

Page 19: ...ote Users have to save and load ACC and PFLAG register by program as interrupt occurrence Example Defining Interrupt Vector The interrupt service routine is following ORG 8 DATA ACCBUF DS 1 Define ACC...

Page 20: ...er program User program JMP START End of user program MY_IRQ The head of interrupt service routine B0XCH A ACCBUF Save ACC in a buffer B0MOV A PFLAG B0MOV PFLAGBUF A Save PFLAG register in a buffer B0...

Page 21: ...TABLE1 DW 0035H To define a word 16 bits data DW 5105H DW 2012H Note The Y register will not increase automatically when Z register crosses boundary from 0xFF to 0x00 Therefore user must take care su...

Page 22: ...V Y TABLE1 M To set lookup table s middle address B0MOV Z TABLE1 L To set lookup table s low address B0MOV A BUF Z Z BUF B0ADD Z A B0BTS1 FC Check the carry flag JMP GETDATA FC 0 INCMS Y FC 1 Y 1 NOP...

Page 23: ...dition instruction Example Jump table ORG 0X0100 The jump table is from the head of the ROM boundary B0ADD PCL A PCL PCL ACC the PCH can t be changed JMP A0POINT ACC 0 jump to A0POINT JMP A1POINT ACC...

Page 24: ...2POINT ACC 2 jump to A2POINT JMP A3POINT ACC 3 jump to A3POINT JMP A4POINT ACC 4 jump to A4POINT If the jump table position is across a ROM boundary 0x00FF 0x0100 the JMP_A macro will adjust the jump...

Page 25: ...d address to end_addr2 CLR Y Set Y to 00H CLR Z Set Z to 00H MOVC B0BSET FC Clear C flag ADD DATA1 A Add A to Data1 MOV A R ADC DATA2 A Add R to Data2 JMP END_CHECK Check if the YZ address the end of...

Page 26: ...al slow Green Sleep Mode Security Enable Enable ROM code Security function Disable Disable ROM code Security function High_Clk_Div Fhosc 4 High clock Fcpu IHRC 4 2MHz Fhosc 8 High clock Fcpu IHRC 8 1M...

Page 27: ...V1 7 2 1 4 DATA MEMORY RAM 256 X 8 bit RAM Address RAM Location Bank 0 000H General purpose area Bank 0 RAM Bank 0 07FH 080H System Register 0FFH 100H End of Bank 0 RAM Bank 1 General purpose area Ban...

Page 28: ...er function control register VREG Voltage Regulators control register CHS PGIA input channel control register AMPM PGIA mode selection register ADCM1 ADC control register1 ADCM2 ADC control register2...

Page 29: ...OMADR1 ROMADR0 R W ROMADRL 0A2H ROMDA15 ROMDA14 ROMDA13 ROMDA12 ROMDA11 ROMDA10 ROMDA9 ROMDA8 W ROMDAH 0A3H ROMDA7 ROMDA6 ROMDA5 ROMDA4 ROMDA3 ROMDA2 ROMDA1 ROMDA0 W ROMDAL 0B8H P07M P06M P05M P04M P0...

Page 30: ...S4PC8 R W STK4H 0F8H S3PC7 S3PC6 S3PC5 S3PC4 S3PC3 S3PC2 S3PC1 S3PC0 R W STK3L 0F9H S3PC11 S3PC10 S3PC9 S3PC8 R W STK3H 0FAH S2PC7 S2PC6 S2PC5 S2PC4 S2PC3 S2PC2 S2PC1 S2PC0 R W STK2L 0FBH S2PC11 S2PC...

Page 31: ...te a immediate data into ACC MOV A 0FH Write ACC data from BUF data memory MOV A BUF The system doesn t store ACC and PFLAG value when interrupt executed ACC and PFLAG data must be saved to other data...

Page 32: ...ithout borrowing rotation with shifting out logic 1 comparison result 0 0 Addition without carry subtraction with borrowing signal rotation with shifting out logic 0 comparison result 0 Bit 1 DC Decim...

Page 33: ...t 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PC PC10 PC9 PC8 PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 After reset 0 0 0 0 0 0 0 0 0 0 0 PCH PCL ONE ADDRESS SKIPPING There are nine in...

Page 34: ...CS BUF0 JMP C0STEP Jump to C0STEP if ACC is not zero C0STEP NOP INCMS instruction INCMS BUF0 JMP C0STEP Jump to C0STEP if BUF0 is not zero C0STEP NOP If the destination decreased by 1 which results un...

Page 35: ...pplications users have to calculate PC value to avoid PCL overflow making PC error and program executing error Note Program counter can t carry to PCH when PCL overflow automatically after executing a...

Page 36: ...R W R W After reset 083H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Z ZBIT7 ZBIT6 ZBIT5 ZBIT4 ZBIT3 ZBIT2 ZBIT1 ZBIT0 Read Write R W R W R W R W R W R W R W R W After reset Example Uses Y Z regi...

Page 37: ...it 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 L LBIT7 LBIT6 LBIT5 LBIT4 LBIT3 LBIT2 LBIT1 LBIT0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Example Uses H L register as the data pointe...

Page 38: ...h byte data of look up table MOVC instruction executed the high byte data of specified ROM address will be stored in R register and the low byte data will be stored in ACC 082H Bit 7 Bit 6 Bit 5 Bit 4...

Page 39: ...out of ACC Example Move 0x12 RAM location data into ACC B0MOV A 12H To get a content of RAM location 0x12 of bank 0 and save in ACC Example Move ACC data into 0x12 RAM location B0MOV 12H A To get a c...

Page 40: ...LL instruction are executed The STKP register is a pointer designed to point active level in order to push or pop up data from stack buffer The STKnH and STKnL are the stack buffers to store program c...

Page 41: ...during interrupt service routine Stack operation is a LIFO type Last in and first out The stack pointer STKP and stack buffer STKnH and STKnL are located in the system register area bank 0 0DFH Bit 7...

Page 42: ...K1H STK1L 3 1 0 0 STK2H STK2L 4 0 1 1 STK3H STK3L 5 0 1 0 STK4H STK4L 6 0 0 1 STK5H STK5L 7 0 0 0 STK6H STK6L 8 1 1 1 STK7H STK7L 8 1 1 0 Stack Over error There are Stack Restore operations correspond...

Page 43: ...s very short but the crystal type is longer Under client terminal application users have to take care the power on reset time for the master terminal requirement The reset timing diagram is as followi...

Page 44: ...OUT RESET 3 4 1 BROWN OUT DESCRIPTION The brown out reset is a power dropping condition The power drops from normal voltage to low voltage by external factors e g EFT interference or external loading...

Page 45: ...ided by LVD detect level The system minimum operating voltage rises when the system executing rate upper even higher than system reset voltage The dead band definition is the system minimum operating...

Page 46: ...eset and the system return to normal mode after reset sequence This method also can improve brown out reset condition and make sure the system to return normal mode If the system reset by watchdog and...

Page 47: ...and the low speed clock can be system clock Fosc The system clock in slow mode is divided by 4 to be the instruction cycle Fcpu Normal Mode High Clock Fcpu Fhosc 4 2MHz Fhosc 8MHz IHRC Fcpu Fhosc 8 1M...

Page 48: ...e run stop Internal low speed RC oscillator is still running Bit 2 CLKMD System high Low clock mode control bit 0 Normal dual mode System clock is high clock 1 Slow mode System clock is internal low c...

Page 49: ...cted by the voltage and temperature of the system In common condition the frequency of the RC oscillator is about 32 KHz at 3 2V The relation between the RC frequency and voltage is as the following f...

Page 50: ...the users can measure system clock speed by software instruction cycle Fcpu This way is useful in RC mode Example Fcpu instruction cycle of external oscillator B0BSET P1M 0 Set P1 0 to be output mode...

Page 51: ...ction Executing Executing Stop Stop T0 timer Active Active Active Inactive Active if T0EN 1 TC0 Timer Active Active Controlled by TC0GN Inactive ADC Active Active Active Stop Active if high clock stil...

Page 52: ...to normal mode The IHRC oscillator is still running B0BCLR FCLKMD To set CLKMD 0 Example Switch slow mode to normal mode The IHRC oscillator stops If internal high clock stop and program want to swit...

Page 53: ...ote During the green mode with T0 wake up function the wakeup pins and T0 can wakeup the system back to the last mode T0 wake up period is controlled by program and T0EN must be set Example Switch nor...

Page 54: ...P TIME When the system is in power down mode sleep mode the high clock oscillator stops When waked up from power down mode MCU waits for 64 internal high speed RC oscillator IHRC clocks as the wakeup...

Page 55: ...e Once interrupt service is executed the GIE bit in STKP register will clear to 0 for stopping other interrupt request On the contrast when interrupt service exits the GIE bit will set to 1 to accept...

Page 56: ...terrupt function Bit 3 URXIEN UART receive interrupt control bit 0 Disable UART receive interrupt function 1 Enable UART receive interrupt function Bit 4 T0IEN T0 timer interrupt control bit 0 Disable...

Page 57: ...IRQ ADC interrupt request controls bit 0 Non ADC interrupt request 1 ADC interrupt request 6 4 GIE GLOBAL INTERRUPT OPERATION GIE is the global interrupt control bit All interrupts start work after th...

Page 58: ...avoid main routine error after interrupt service routine finishing Note To save load ACC data users must be B0XCH instruction or else the PFLAG register might be modified by ACC operation Example Stor...

Page 59: ...DGE P01G1 P01G0 P00G1 P00G0 Read Write R W R W R W R W After reset 1 0 1 0 Bit 4 3 P00G 1 0 P0 0 interrupt trigger edge control bits 00 reserved 01 rising edge 10 falling edge 11 rising falling bi dir...

Page 60: ...the priority for these interrupt requests Two is using IEN and IRQ flags to decide which interrupt to be executed Users have to check interrupt control bit and interrupt request flag in interrupt rou...

Page 61: ...URXCHK Jump check to next interrupt B0BTS0 FUTXIRQ Check UTXIRQ JMP INTUTX Jump to UART TX interrupt service routine INTURXCHK Check URX interrupt request B0BTS1 FURXIEN Check URXIEN JMP INT_EXIT Jump...

Page 62: ...6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3M P37M P36M P35M P34M P33M P32M P31M P30M Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0 0 0 Bit 7 0 PnM 7 0 Pn mode control bits n 0 1 0 Pn...

Page 63: ...rts to be LCD mode CLR P3SEG Set P3 ports to be LCD mode MOV A 0FFh B0MOV P2SEG A Set P2 ports to be I O mode MOV A 0Fh B0MOV P3SEG A Set P34 P37 ports to be LCD mode Set P30 P33 ports to be I O mode...

Page 64: ...ite W W After reset 0 0 0DDH Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P2UR P27R P26R P25R P24R P23R P22R P21R P20R Read Write W W W W W W W W After Reset 0 0 0 0 0 0 0 0 0DEH Bit 7 Bit 6 Bit 5...

Page 65: ...7 P26 P25 P24 P23 P22 P21 P20 Read Write R W R W R W R W R W R W R W R W After Reset 0 0 0 0 0 0 0 0 0D3H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 P3 P37 P36 P35 P34 P33 P32 P31 P30 Read Write...

Page 66: ...rrent sink grounding influence ADC operation 32768Hz 20p ON OFF Key1 Key2 20p Optional for RTC Clock Weight Scale Application Circuit LQFP48 Pin LED4 8 10uf 1uf LED BLE Module VBAT SN8P2977 SEG1 P36 S...

Page 67: ...chdog Overflow Time 3 3V 32KHz 512ms 1 Note 1 If watchdog is Always_On mode it keeps running event under power down mode or green mode 2 For S8KD ICE simulation clear watchdog timer using RST_WDT macr...

Page 68: ...service routine That can improve main routine fail Clearing watchdog timer program is only at one part of the program This way is the best structure to enhance the watchdog timer function Example An o...

Page 69: ...can be green mode wake up time as T0ENB 1 System will be wake up by T0 time out Fcpu T0 Rate Fcpu 2 Fcpu 256 T0ENB CPUM0 1 T0C 8 Bit Binary Up Counting Counter T0 Time Out Load Internal Data Bus T0ENB...

Page 70: ...Y CO LTD Page 70 Version 1 7 Bit 6 4 T0RATE 2 0 T0 internal clock select bits 000 fcpu 256 001 fcpu 128 110 fcpu 4 111 fcpu 2 Bit 7 T0ENB T0 counter control bit 0 Disable T0 timer 1 Enable T0 timer No...

Page 71: ...Fcpu 64 T0C initial value 256 T0 interrupt interval time input clock 256 10ms 8MHz 8 64 256 10 2 8 106 8 64 100 64H The basic timer table interval time of T0 T0RATE T0CLOCK High speed mode Fcpu 8MHz...

Page 72: ...0 interrupt function is disabled B0BCLR FT0IRQ T0 interrupt request flag is cleared Set T0 timer rate MOV A 0xxx0000b The T0 rate control bits exist in bit4 bit6 of T0M The value is from x000xxxxb x11...

Page 73: ...b B0MOV T0M A Set T0 clock source from RTC B0BSET FT0TB Select T0 RTC clock source Set T0 interrupt interval time CLR T0C Clear T0C value CLR OLDT0C Clear OLDT0C value CLR NEWT0C Clear NEWT0C value CL...

Page 74: ...r T0IRQFLAG CALL DELAY Call delay time over 1 32 768ms for RTC limit B0BCLR FT0IRQ Clear FT0IRQ CALL UPDATE_TIME Update time EXIT_CKTT0FLAG RET Exit sub routing Into green mode before CALL CKT_T0CVAL...

Page 75: ...ervice TC0 overflow time is 0xFF to 0X00 normally Under PWM mode TC0 overflow is decided by PWM cycle controlled by ALOAD0 and TC0OUT bits The main purposes of the TC0 timer is as following 8 bit prog...

Page 76: ...function 1 Enable P1 1 is output TC0OUT signal Bit 2 ALOAD0 Auto reload control bit Only valid when PWM0OUT 0 0 Disable TC0 auto reload function 1 Enable TC0 auto reload function Bit 3 TC0CKS TC0 clo...

Page 77: ...e RTC T0 clock source from Fcpu 1 Enable RTC Bit 1 TC0GN Enable TC0 Green mode wake up function 0 Disable 1 Enable Bit 2 TC0X8 TC0 internal clock source control bit 0 TC0 internal clock source is Fcpu...

Page 78: ...cpu 64 TC0C initial value N TC0 interrupt interval time input clock 256 10ms 8MHz 8 64 256 10 2 8 106 8 64 100 64H The basic timer table interval time of TC0 TC0X8 0 TC0RATE TC0CLOCK High speed mode F...

Page 79: ...PGIA 24 bit ADC SONiX TECHNOLOGY CO LTD Page 79 Version 1 7 100 Fosc 8 0 256 ms 1 us 62 5 ms 244 141 us 101 Fosc 4 0 128 ms 0 5 us 31 25 ms 122 07 us 110 Fosc 2 0 064 ms 0 25 us 15 625 ms 61 035 us 1...

Page 80: ...er reset 0 0 0 0 0 0 0 0 The equation of TC0R initial value is as following TC0R initial value N TC0 interrupt interval time input clock N is TC0 overflow boundary number TC0 timer overflow time has s...

Page 81: ...quency waveform is as following 1 2 3 4 1 2 3 4 TC0 Overflow Clock TC0OUT Buzzer Output Clock Example Setup TC0OUT output from TC0 to TC0OUT P1 1 The external high speed clock is 8MHz Fcpu Fosc 8 The...

Page 82: ...R FTC0CKS Select TC0 internal clock source or B0BSET FTC0CKS Select TC0 external clock source Select TC0 Fcpu Fosc internal clock source B0BCLR FTC0X8 Select TC0 Fcpu internal clock source or B0BSET F...

Page 83: ...ister TC0R When the reference register value TC0R is equal to the counter value TC0C the PWM output goes low When the counter reaches zero the PWM output is forced high The ratio duty of the PWM0 outp...

Page 84: ...illator clock TC0 rate is Fcpu 4 The TC0RATE2 TC0RATE1 110 TC0C TC0R 30 MOV A 01100000B B0MOV TC0M A Set the TC0 rate to Fcpu 4 MOV A 30 Set the PWM duty to 30 256 B0MOV TC0C A B0MOV TC0R A B0BSET FPW...

Page 85: ...0R the PWM will output logic Low If TC0C is changed in certain period the PWM duty will change immediately If TC0R is fixed all the time the PWM waveform is also the same TC0C overflow and TC0IRQ set...

Page 86: ...e baud rate 9 2 UART OPERATION The UART RX P05 and TX P04 pins are shared with GPIO When UART enables RXDEN 1 TXDEN 1 the UART shared pins transfers to UART purpose and disable GPIO function automatic...

Page 87: ...bit7 Parity Stop Idle Status Idle Status UART Transfer Format with Parity Bit Start Stop Idle Status Idle Status bit0 bit1 bit2 bit3 bit4 bit5 bit6 bit7 UART Transfer Format without Parity Bit Bus Id...

Page 88: ...it6 URX Pin Start If the host s UART baud rate isn t match to receiver terminal the received pocket is error But it is not easy to differentiate the pocket is correct or not because the received error...

Page 89: ...equation is as following UART Baud Rate 1 2 Fuart 1 256 URCR bps Fhosc 8MHz Baud Rate UART Pre scaler URS 2 0 URCR Hex UART Baud Rate Accuracy 1200 Fhosc 16 100b 30 1202 0 16 2400 Fhosc 16 100b 98 240...

Page 90: ...Enable UART RX parity bit function The data stream includes parity bit Bit 7 URXEN UART RX control bit 0 Disable UART RX URX pin is GPIO mode or returns to GPIO status 1 Enable UART RX URX pin exchang...

Page 91: ...UTXBZ bits 9 8 UART TRANSMITTER CONTROL REGISTER 0E5H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UTXD UTXD7 UTXD6 UTXD5 UTXD4 UTXD3 UTXD2 UTXD1 UTXD0 Read Write R W R W R W R W R W R W R W R W A...

Page 92: ...re scaler URS 2 0 B0MOV URRX A MOV A value2 Set UART baud rate 8 bit buffer B0MOV URCR A Enable UART TX pin B0BSET FUTXEN Enable UART TX function and UART TX pin Enable UART TX interrupt function B0BC...

Page 93: ...controllable by setting the BZRCKS 1 0 register Buzzer frequency Table BZRCKS1 BZRCKS0 Buzzer frequency Note 0 0 0 98k Hz Buzzer clock source From IHRC 8MHz 0 1 1 96k Hz 1 0 3 9k Hz 1 1 7 8k Hz 10 2...

Page 94: ...additional external bias circuit in R type LCD driver and adjusted by setting internal charge pump in C type LCD driver 11 2 LCD TIMING LCD Timing Table LCDCLK Clock Source LCDRATE LCD Clock Frame LCD...

Page 95: ...e Waveform 1 4 duty 1 3 bias VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD VLCD VSS 1 3 VLCD 2 3 VLCD COM0 COM1...

Page 96: ...bit 00 C Type LCD Mode 01 R Type LCD Mode 10 ISP Mode 11 LCD Mode All OFF Bit7 LCDBNK LCD blank control bit 0 Normal display 1 All of the LCD dots off Note1 LCD disable in green or sleep mode LCDENB i...

Page 97: ...it 0 VLCD Pin no discharge 1 VLCD Pin discharge After the end of ISP for discharging VLCD 7 5V down to VDD Bit 7 6 VAR 1 0 VLCD pump ripple Control bit C Type R Type VAR 1 0 Pump Vripple Power Saving...

Page 98: ...CD charge pump voltage level is following VLCD voltage In C type LCD mode the LCDMOD 1 0 bits f LCDM1 register must be 0 The following are shown the 1 3 and 1 2 bias C Type LCD application circuit and...

Page 99: ...er LCD power VLCD is auto connected to VDD via internal circuit V3 and V2 bias voltage source from internal voltage division by resistors The following diagram shows the connection of 1 4 duty with 1...

Page 100: ...LTD Page 100 Version 1 7 1 4 duty with 1 2 bias V3 V2 VLCD LCDMOD 1 0 VDD 35 k SN8P2977 1uF LCDBIAS 1 Short 35 k LCD current consumption 2 35k VLCD Note_1 In R Type LCD driver mode VLCD power is auto...

Page 101: ...2 00H 3 SEG 1 01H 0 01H 1 01H 2 01H 3 SEG 2 02H 0 02H 1 02H 2 02H 3 SEG 3 03H 0 03H 1 03H 2 03H 3 SEG 15 0FH 0 0FH 1 0FH 2 0FH 3 Example Enable LCD function Set the LCD control bit LCDEN and program L...

Page 102: ...0 0 0 0 0A1H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ROMADRL ROMADR7 ROMADR6 ROMADR5 ROMADR4 ROMADR3 ROMADR2 ROMADR1 ROMADR0 Read Write R W R W R W R W R W R W R W R W After reset 0 0 0 0 0 0...

Page 103: ...et ISP Address Start Address 0x01F0h MOV A 0F0H B0MOV ROMADRL A Move Low Byte Address to ROMADRL MOV A 01H B0MOV ROMADRH A Move High Byte Address to ROMADRH Load data for ISP MOV A 12H Data 0x1234 B0M...

Page 104: ...ogrammable gain instrumentation amplifier PGIA with selectable gains of 1x 4x 8x 16x 32x 64x 128x and 200x in the ADC to accommodate these applications 13 2 ANALOG INPUT Following diagram illustrates...

Page 105: ...sable Regulator and AVE Output voltage 1 Enable Regulator and AVE Output voltage Note When AVE enable AVE set 1 5V 2 0V AVE pin have to connect 1uf capacitors to ground Bit 4 3 AVESEL 1 0 Regulator AV...

Page 106: ...4 100 AVE 111 Gnd MUXN AI1 000 AVE 100 Temp 110 2 8 VDD 101 AI2 001 AI3 010 AI4 011 Gnd 111 MUXP AI1 000 AVE 100 Temp 110 3 8 VDD 101 AI2 001 AI3 010 AI4 011 Gnd 111 MUXN 2 0 000 AI1 101 VDD_DET 110 T...

Page 107: ...0 01110111 CHS 7 0 01100110 PGIA 1x1 AMPEN 0 CHS 7 0 01010101 PGIA 1x1 AMPEN 0 PGIA AVE ADC X X REF REF AI3 CHS 7 0 00100100 PGIA AVE ADC X X REF REF AI4 CHS 7 0 00110100 Note_1 V AI1 AI2 AI1 voltage...

Page 108: ...l bit 0 Disable PGIA function PGIA input signal by pass to ADC 1 Enable PGIA function Note_1 In Temperature detection mode or VDD detection mode PGIA Gain always set 1x GS0 2 0 000 application the AI...

Page 109: ...ference data not real air temperature For precision application please use external thermistor sensor In 25C V TS will be about 1 056V typically and if temperature rise 10 V TS will decrease about 17...

Page 110: ...re PGIA working Example PGIA channel change PGIA_Setting MOV A 00000001B B0MOV CHS A V X X Output V AI1 AI2 MOV A 00011100B PGIA chopper Enable Gain 128x B0MOV AMPM A PGIA chopper Freq 31 25kHz PGIA_E...

Page 111: ...28 010 256 011 1024 100 4096 101 8192 110 16384 111 32768 ADC Offset OFSEL 1 0 00 75 Vref 01 50 Vref 10 25 Vref 11 0 Vref Internal Vref RVS 3 0 0100 0 36V 0101 0 60V 0110 0 84V 0111 1 20V RVS 3 0 When...

Page 112: ...an be adjusted offset level by subtraction or addition function to increase the signal operation range of ADC in weigh scales application ADC Offset function is controlled by OFSEL 1 0 bits in registe...

Page 113: ...3 0 Vref source IRVS 3 0 Vref source VBG 1 2V External Input 10xx 0 8V 11xx R R Note 1 Vref source from AVE 1 5V 2 0V AVE pin connect 1uf capacitors to ground 2 When CHS 0x66h Vref voltage have to set...

Page 114: ...d ADCDLL 0 ADCDH ADCDL and ADCDLL conversion data are not ready Note 1 ADC Output Word Rate WR ADC Clock OSR Note 2 Adjust ADC clock ADCKS and OSR can get suitable ADC output word rate Note 3 For High...

Page 115: ...decimal Decimal Value 0x7FFFFH 524287 0x40000H 262144 0x10000H 65536 0x00002H 2 0x00001H 1 0x00000H 0 0xFFFFFH 1 0xFFFFEH 2 0xF0000H 65536 0xC0000H 262144 0x80000H 524288 Note 1 ADCDH 7 0 ADCDM 7 0 an...

Page 116: ...1 32768 7 6Hz 15 9 18 6 0 215uV 0 033uV 128 x 2 32768 7 6Hz 15 17 7 0 200uV 0 030uV 200 x 1 32768 7 6Hz 15 3 18 0 208uV 0 032uV 128 x 1 16384 15 3Hz 15 5 18 2 0 283uV 0 043uV 128 x 1 8192 31Hz 14 9 17...

Page 117: ...DC chopper 31 25KHz B0MOV ADCM1 A ADC Reference voltage internal 0 84V ADC_Gain 1x MOV A 01110110B B0MOV ADCM2 A Set ADC clock 250kHz OSR 32768 offset 0V B0BSET FADCENB Enable ADC function ADC_Wait B0...

Page 118: ...GIA buffer off and PGIA chopper 31 25KHz B0BCLR FAMPENB Disable PGIA function V X X Output V VDD VDD x 1 ADC_Init MOV A 01101000B ADC chopper 31 25KHz B0MOV ADCM1 A ADC Reference voltage internal 0 84...

Page 119: ...P ADC_Wait Wait for Bit DRDY 1 ADC_Read B0BCLR FDRDY Output ADC conversion word B0MOV A ADCDH B0MOV Data_H_Buf A Move ADC conversion High byte to Data Buffer B0MOV A ADCDM B0MOV Data_M_Buf A Move ADC...

Page 120: ...FBGRENB Disable Band Gap Voltage SleepMode System into Sleep mode Macro Note 1 Please set ADC relative registers first before enable ADC function Note 2 Before enable ADC function please set analog f...

Page 121: ...TO 1 1xxx P10 1 2V LBTO 1 13 7 1 LBTM Low Battery Detect Register 095H Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LBTM P11IO LBTSEL3 LBTSEL2 LBTSEL1 LBTSEL0 LBTO LBTENB R W R W R W R W R W R W R...

Page 122: ...8V Note_1 Get LBTO 1 more 10 times in a raw every certain period ex 20 ms or more to make sure the Low Battery signal is stable Note_2 Before enable LBT function please set LBT function and wait 50us...

Page 123: ...E CAVE A I2 CAI1 AI2 A I1 AI4 R CAI3 R AI4 R AI3 R Setting AI1 AI2 AI1 voltage AI2 voltage External Vref source from AVDDR Capacitor Table Power type AI1 AI2 AI3 R AI4 R AVDDR AVE VLCD AVDD DVDD CAI1...

Page 124: ...ors the maximum output current will be limited 5mA typically Note_2 AVE connect 1uf capacitors the maximum output current will be limited 5mA typically Note_3 When MCU VDD power sources from AA AAA dr...

Page 125: ...lock 1uf LED BLE Module VBAT SN8P2977 SEG1 P36 SEG0 P37 COM3 COM2 COM1 COM0 VLCD VPP AVDDR AVE AVSS AVDD NC AI1 AI2 AI3 R AI4 R NC NC NC NC P10 LBT0 P11 PWM0 P00 INT0 P01 INT1 P21 SEG14 P20 SEG15 NC N...

Page 126: ...Clock 1uf LED BLE Module VBAT SN8P2977 SEG1 P36 SEG0 P37 COM3 COM2 COM1 COM0 VLCD VPP AVDDR AVE AVSS AVDD NC AI1 AI2 AI3 R AI4 R NC NC NC NC P10 LBT0 P11 PWM0 P00 INT0 P01 INT1 P21 SEG14 P20 SEG15 NC...

Page 127: ...XOR A M A A xor M 1 XOR M A M A xor M 1 N XOR A I A A xor I 1 SWAP M A b3 b0 b7 b4 M b7 b4 b3 b0 1 P SWAPM M M b3 b0 b7 b4 M b7 b4 b3 b0 1 N R RRC M A RRC M 1 O RRCM M M RRC M 1 N C RLC M A RLC M 1 E...

Page 128: ...emulation speed at 3 3V 2 MIPS e g Fcpu Fhosc 4 Use SN8P2977 EV KIT to emulation Analog Function Note S8ICE1K doesn t support SN8P2977 serial emulation 16 1 2 OTP Writer MP Pro Writer ON OFF line oper...

Page 129: ...er 1 VDD DVDD AVDD 27 20 23 13 2 GND DVSS AVSS 40 19 33 12 3 CLK PGCLK P0 1 30 26 4 CE 5 PGM OTPCLK P0 2 31 27 6 OE ShiftData P0 3 32 28 7 D1 8 D0 9 D3 10 D2 11 D5 12 D4 13 D7 14 D6 15 VDD DVDD AVDD 2...

Page 130: ...G03 P34 4 SEG02 P35 5 SEG01 P36 6 SEG00 P37 7 COM3 8 COM2 9 COM1 10 COM0 11 VLCD VPP 12 NC 13 NC 14 AVDDR 15 AVE 16 AVSS 17 AVDD 18 AI1 19 AI2 20 R AI3 21 R AI4 22 NC 23 NC 24 P1 0 25 P1 1 26 NC 27 P0...

Page 131: ...d to simulate the program code using the software or the ICE itself On the other hand when executing the program and monitoring the RAM status users can user various functions such as Breakpoint Singl...

Page 132: ...ontroller with Regulator PGIA 24 bit ADC SONiX TECHNOLOGY CO LTD Page 132 Version 1 7 16 4 3 SN8P2977 EV Board DESCRIPTION Sonix provides SN8P2977 EV board for all functions emulation shown in FIG 1 F...

Page 133: ...nector 5 J2 LCD COM SEG connect Pin 6 J3 J7 Analog Differential AI AI input Pin 7 SW3 Switch to ICE position when EV Board connect to ICE When separate ICE and Ev board switch SW3 to DEMO position or...

Page 134: ...istor disable Vin Vdd 2 uA I O port source current sink current P0 IoH Vop Vdd 0 5V 7 10 mA P1 IoH 15 20 P2 IoH 15 20 P3 IoH 12 20 P0 IoL Vop Vss 0 5V 8 10 P1 IoL 45 60 P2 IoL 45 60 P3 IoL 45 60 INT0...

Page 135: ...ent consumption IDD_PGIA Run mode 2 4V 150 uA Power down current IPDN Stop mode 2 4V 0 1 uA Input offset voltage Vos 25 uV Bandwidth BW 5 kHz PGIA Gain Range Gain VDD 2 4V PGIA x 128 110 128 150 Gain...

Page 136: ...INFORMATION 18 1 DIP 48 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 220 5 588 A1 0 015 0 381 A2 0 150 0 155 0 160 3 810 3 937 4 064 D 2 400 2 450 2 550 60 960 62 230 64 770 E 0 600 15 240 E1 0 540...

Page 137: ...5 0 102 0 110 2 413 2 591 2 794 A1 0 008 0 012 0 016 0 203 0 305 0 406 A2 0 089 0 094 0 099 2 261 2 388 2 515 b 0 008 0 010 0 030 0 203 0 254 0 762 C 0 008 0 203 D 0 620 0 625 0 630 15 748 15 875 16 0...

Page 138: ...lator PGIA 24 bit ADC SONiX TECHNOLOGY CO LTD Page 138 Version 1 7 18 3 LQFP 48 PIN SYMBOLS MIN NOR MAX mm A 1 6 A1 0 05 0 15 A2 1 35 1 45 c1 0 09 0 16 D 9 00 BSC D1 7 00 BSC E 9 00 BSC E1 7 00 BSC e...

Page 139: ...cal Max inch mm A 0 028 0 030 0 031 0 70 0 80 0 90 A1 0 0 001 0 002 0 0 02 0 05 A3 0 008 REF 0 20 REF b 0 006 0 008 0 010 0 15 0 20 0 25 D 0 157 BSC 4 00 BSC E 0 157 BSC 4 00 BSC e 0 016 BSC 0 40 BSC...

Page 140: ...0 047 1 2 A1 0 000 0 006 0 00 0 15 A2 0 031 0 039 0 041 0 80 1 00 1 05 b 0 007 0 012 0 19 0 30 c 0 004 0 008 0 09 0 20 D 0 378 0 382 0 386 9 60 9 70 9 80 E 0 252 BSC 6 40 BSC E1 0 169 0 173 0 177 4 3...

Page 141: ...A1 0 004 0 006 0 010 0 100 0 150 0 250 A2 0 059 1 500 b 0 008 0 010 0 012 0 200 0 254 0 300 c 0 007 0 008 0 010 0 180 0 203 0 250 D 0 337 0 341 0 344 8 560 8 660 8 740 E 0 228 0 236 0 244 5 800 6 000...

Page 142: ...7 18 7 SOP 18 PIN SYMBOLS MIN NOR MAX MIN NOR MAX inch mm A 0 093 0 099 0 104 2 362 2 502 2 642 A1 0 004 0 008 0 012 0 102 0 203 0 305 D 0 447 0 455 0 463 11 354 11 557 11 760 E 0 291 0 295 0 299 7 3...

Page 143: ...on 1 7 18 8 SOP 16 PIN SYMBOLS Min Typical Max Min Typical Max inch mm A 0 069 1 75 A1 0 004 0 010 0 10 0 25 A2 0 049 1 25 b 0 012 0 020 0 31 0 51 c 0 004 0 010 0 10 0 25 D 0 39BSC 9 90BSC E 0 236BSC...

Page 144: ...8 bit MCU production line This note listed the production definition of all 8 bit MCU for order or obtains information This definition is only for Blank OTP MCU 19 2 MARKING INDETIFICATION SYSTEM Titl...

Page 145: ...e SN8P2977FG OTP 2977 LQFP48 0 70 Green Package SN8P2975JG OTP 2977 QFN32 0 70 Green Package SN8P2974TG OTP 2977 TSSOP28 0 70 Green Package SN8P29731XG OTP 2977 SSOP20 0 70 Green Package SN8P2972SG OT...

Page 146: ...njury or death may occur Should Buyer purchase or use SONIX products for any such unintended or unauthorized application Buyer shall indemnify and hold SONIX and its officers employees subsidiaries af...

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