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Silicon Laboratories Si5316 Series, Reference Manual

The Silicon Laboratories Si5316 Series Family Reference Manual is your comprehensive guide to understanding and utilizing our cutting-edge product. This invaluable manual is available for download, free of charge, at manualshive.com. Unlock the full potential of your Si5316 with this essential manual.

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Si53xx-RM

Rev. 0.52

93

For cases where phase skew is required, see Section “7.7. Output Phase Adjust (Si5326, Si5368)” for more details
on controlling the sync input to sync output phase skew via the 

FSYNC_SKEW

[16:0] bits. See Section

 

“8.2. Output

Clock Drivers” for information on the FS_OUT signal format, pulse width, and active logic level control.

7.8.2. FSYNC Skew Control (Si5368)

When CKIN3 and CKIN4 are configured as frame sync inputs (

CK_CONFIG_REG

= 1), phase skew of the sync

input active edge to FS_OUT active edge is controllable via the 

FSYNC_SKEW

[16:0] register bits. Skew control

has a resolution of 1/f

CKOUT2

 and a range of 131,071/f

CKOUT2

. The entered skew value must be less than the

period of CKIN3, CKIN4, and FS_OUT.

The skew should not be changed more than once per FS_OUT period. If a FSYNC realignment is being made, the
skew should not be changed until the realignment is complete. The skew value and the FS_OUT pulse width
should not be changed within the same FS_OUT period.

Before writing the three bytes needed to specify a new 

FSYNC_SKEW

[16:0] value, the user should set the register

bit 

FSKEW_VALID

= 0. This causes the alignment state machine to keep using the previous 

FSYNC_SKEW

[16:0]

value, ignoring the new register values as they are being written. Once the new 

FSYNC_SKEW

[16:0] value has

been completely written, the user should set 

FSKEW_VALID

= 1 at which time the alignment state machine will

read the new skew alignment value. Note that when the new 

FSYNC_SKEW

[16:0] value is used, a phase step will

occur in FS_OUT.

7.8.3. Including FSYNC Inputs in Clock Selection (Si5368)

The frame sync inputs, CKIN3 and CKIN4, are both monitored for loss-of-signal (

LOS3_INT

 and 

LOS4_INT

)

conditions. To include these LOS alarms in the input clock selection algorithm, set 

FSYNC_SWTCH_REG

= 1.  The

LOS3_INT

 is logically ORed with 

LOS1_INT

 and 

LOS4_INT

  is  ORed  with 

LOS2_INT

 as inputs to the clock

selection state machine. If it is desired not to include these alarms in the clock selection algorithm, set

FSYNC_SWTCH_REG

= 0. The frequency offset (FOS) alarms for CKIN1 and CKIN2 can also be included in the

state machine decision making as described in Section “7.11. Alarms (Si5319, Si5324, Si5325, Si5326, Si5327,
Si5367, Si5368, Si5369, Si5374, Si5375)”; however, in frame sync mode (

CK_CONFIG_REG

= 1), the FOS alarms

for CKIN3 and CKIN4 are ignored.

7.8.4. FS_OUT Polarity and Pulse Width Control (Si5368)

Additional output controls are available for FS_OUT. The active polarity of FS_OUT is set via the 

FS_OUT_POL

register bit and the active duty cycle is set via the 

FSYNC_PW

[9:0] register. Pulse width settings have a resolution

of 1/f

CKOUT2

, and a 50% duty cycle setting is provided. Pulse width settings can range from 1 to (NC5-1) CKOUT2

periods, providing the full range of pulse width possibilities for a given NC5 divider setting.

The FS_OUT pulse should not be changed more than once per FS_OUT period. If a FSYNC realignment is being
made, the pulse width should not be changed until the realignment is complete. The FS_OUT pulse width and the
skew value should not be changed within the same FS_OUT period.

Before writing a new value into 

FSYNC_PW

[9:0], the user should set the register bit 

FPW_VALID

= 0. This causes

the FS_OUT pulse width state machine to keep using the previous 

FSYNC_PW

[9:0] value, ignoring the new

register values as they are being written. Once the new 

FSYNC_PW

[9:0] value has been completely written, the

user should set 

FPW_VALID

= 1, at which time the FS_OUT pulse width state machine will read the new pulse

width value.

Writes to 

NC5_LS

 should be treated the same as writes to 

FSYNC_PW

. Thus, all writes to 

NC5_LS

 should occur

only when 

FPW_VALID = 0

. Any such writes will not take effect until 

FPW_VALID = 1

.

Note that f

CKOUT2

 must be less than or equal to 710 MHz when CK_CONFIG_REG = 1; otherwise, the FS_OUT

buffer and NC5 divider must be disabled.

7.8.5. Using FS_OUT as a Fifth Output Clock (Si5368)

In applications where the frame synchronization functionality is not needed (

CK_CONFIG_REG

= 0), FS_OUT can

be used as a fifth clock output. In this case, no realignment requests should be made to the NC5 divider (hold

FS_ALIGN

= 0 and 

FSYNC_ALIGN_REG

= 0). Output pulse width and polarity controls for FS_OUT are still

available as described above. The 50% duty cycle setting would be used to generate a typical balanced output
clock.

Summary of Contents for Si5316 Series

Page 1: ... 12 Copyright 2012 by Silicon Laboratories Si53xx RM ANY FREQUENCY PRECISION CLOCKS Si5316 Si5319 Si5322 Si5323 Si5324 Si5325 Si5326 Si5327 Si5365 Si5366 Si5367 Si5368 Si5369 Si5374 Si5375 FAMILY REFERENCE MANUAL ...

Page 2: ...Si53xx RM 2 Rev 0 52 ...

Page 3: ...i5322 Si5323 Si5365 Si5366 49 6 1 Clock Multiplication Si5316 Si5322 Si5323 Si5365 Si5366 49 6 1 1 Clock Multiplication Si5316 49 6 1 2 Clock Multiplication Si5322 Si5323 Si5365 Si5366 51 6 1 3 CKOUT3 and CKOUT4 Si5365 and Si5366 63 6 1 4 Loop bandwidth Si5316 Si5322 Si5323 Si5365 Si5366 63 6 1 5 Jitter Tolerance Si5316 Si5323 Si5366 63 6 1 6 Narrowband Performance Si5316 Si5323 Si5366 63 6 1 7 In...

Page 4: ...11 DSPLLsim Configuration Software 74 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 75 7 1 Clock Multiplication 75 7 1 1 Jitter Tolerance Si5319 Si5324 Si5325 Si5326 Si5327 Si5368 Si5369 Si5374 and Si5375 75 7 1 2 Wideband Parts Si5325 Si5367 75 7 1 3 Narrowband Parts Si5319 Si5324 Si5326 Si5327 Si5368 Si5369 Si5374 Si5375 76 7 1 4 Loop Ban...

Page 5: ...i5374 Si5375 94 7 9 1 Disabling CKOUTn 94 7 9 2 LVPECL TQFP Output Signal Format Restrictions at 3 3 V Si5367 Si5368 Si5369 94 7 10 PLL Bypass Mode Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 95 7 11 Alarms Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 95 7 11 1 Loss of Signal Alarms Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si...

Page 6: ...dix B Frequency Plans and Jitter Performance Si5316 Si5319 Si5323 Si5324 Si5326 Si5327 Si5366 Si5368 Si5369 Si5374 Si5375 121 Appendix C Typical Phase Noise Plots 126 Appendix D Alarm Structure 144 Appendix E Internal Pullup Pulldown by Pin 147 Appendix F Typical Performance Bypass Mode PSRR Crosstalk Output Format Jitter 154 Appendix G Near Integer Ratios 162 Appendix H Jitter Attenuation and Loo...

Page 7: ...Voltage Characteristics 31 Figure 17 Rise Fall Time Characteristics 31 Figure 18 SPI Timing Diagram 37 Figure 19 Frame Synchronization Timing 38 Figure 20 Any Frequency Precision Clock DSPLL Block Diagram 45 Figure 21 Clock Multiplication Circuit 46 Figure 22 PLL Jitter Transfer Mask Template 47 Figure 23 Jitter Tolerance Mask Template 48 Figure 24 Si5316 Divisor Ratios 50 Figure 25 Wideband PLL D...

Page 8: ...85 MHz Crystal 124 Figure 64 622 08 MHz Output with a 40 MHz Crystal 125 Figure 65 155 52 MHz In 622 08 MHz Out 126 Figure 66 155 52 MHz In 622 08 MHz Out Loop BW 7 Hz Si5324 127 Figure 67 19 44 MHz In 156 25 MHz Out Loop BW 80 Hz 128 Figure 68 19 44 MHz In 156 25 MHz Out Loop BW 5 Hz Si5324 129 Figure 69 27 MHz In 148 35 MHz Out Light Trace BW 6 Hz Dark Trace BW 110 Hz Si5324 130 Figure 70 61 44 ...

Page 9: ... Jitter 167 Figure 94 RF Generator Si5326 Si5324 10 kHz Jitter 168 Figure 95 Vdd Plane 169 Figure 96 Ground Plane and Reset 170 Figure 97 Output Clock Routing 171 Figure 98 OSC_P OSC_N Routing 172 Figure 99 Si5374 Si5375 DSPLL A 174 Figure 100 Si5374 Si5375 DSPLL B 175 Figure 101 Si5374 Si5375 DSPLL C 176 Figure 102 Si5374 Si5375 DSPLL D 177 Figure 103 178 Figure 104 179 Figure 105 Wide View of Ji...

Page 10: ...rol DIV34 63 Table 20 Si5316 Si5322 and Si5323 Pins and Reset 65 Table 21 Si5365 and Si5366 Pins and Reset 65 Table 22 Manual Input Clock Selection Si5316 Si5322 Si5323 AUTOSEL L 66 Table 23 Manual Input Clock Selection Si5365 Si5366 AUTOSEL L 66 Table 24 Automatic Manual Clock Selection 67 Table 25 Clock Active Indicators AUTOSEL M or H Si5322 and Si5323 67 Table 26 Clock Active Indicators AUTOSE...

Page 11: ...Format Measurements1 2 108 Table 59 Approved Crystals 118 Table 60 XA XB Reference Sources and Frequencies 118 Table 61 Jitter Values for Figure 61 122 Table 62 Jitter Values for Figure 62 123 Table 63 Jitter Values for Figure 74 135 Table 64 Jitter Values for Figure 75 136 Table 65 Jitter Values for Figure 76 137 Table 66 Jitter Values for Figure 77 138 Table 67 Jitter Values for Figure 80 141 Ta...

Page 12: ...requencies The Si5316 Si5319 Si5323 Si5326 Si5327 Si5366 Si5368 and Si5369 support a digitally programmable loop bandwidth that can range from 60 Hz to 8 4 kHz An external 37 41 MHz 55 61 MHz 109 125 5 MHz or 163 180 MHz reference clock or a low cost 114 285 MHz 3rd overtone crystal is required for these devices to enable ultra low jitter generation and jitter attenuation See Appendix A Narrowband...

Page 13: ...re a common I2 C bus and a common XA XB jitter reference oscillator The Si5375 consists of four one input and one output DSPLLs The Si5374 consists of four two input and two output DSPLLs with very low loop bandwidth The Any Frequency Precision Clocks have differential clock output s with programmable signal formats to support LVPECL LVDS CML and CMOS loads If the CMOS signal format is selected ea...

Page 14: ...6 mm 36 QFN Si5324 I2 C SPI 1PLL 2 2 0 002 710 0 002 1417 0 3 ps 4 Hz to 525 Hz 6x6 mm 36 QFN Si5326 I2C SPI 1PLL 2 2 0 002 710 0 002 1417 0 3 ps 60 Hz to 8 kHz 6x6 mm 36 QFN Si5327 I2C SPI 1PLL 2 2 0 002 710 0 002 808 0 5 ps 4 Hz to 525 Hz 6x6 mm 36 QFN Si5366 Pin 1PLL 4 5 0 008 707 0 008 1050 0 3 ps 60 Hz to 8 kHz 14x14 mm 100 TQFP Si5368 I2C SPI 1PLL 4 5 0 002 710 0 002 1417 0 3 ps 60 Hz to 8 k...

Page 15: ...us indicator FOS is not supported Table 2 Product Selection Guide Si5322 25 65 67 Device Clock Inputs Clock Outputs P Control Max Input Freq MHz 1 Max Output Frequency MHz Jitter Generation 12 kHz 20 MHz LOS Hitless Switching FOS Alarm LOL Alarm FSYNC Realignment 36 Lead 6 mm x 6 mm QFN 100 Lead 14 x 14 mm TQFP 1 8 2 5 3 3 V Operation 1 8 2 5 V Operation Low Jitter Precision Clock Multipliers Wide...

Page 16: ...imum of 710 MHz in the 622 MHz range The DSPLL loop bandwidth is digitally selectable providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5316 is ideal for providing jitter attenuation in high performance timing applications See 6 Pin Control Parts Si5316 Si5322 Si5323 Si5365 Si5366 on page 49 for a complete description Figure 1 ...

Page 17: ...DSPLL technology which provides any frequency synthesis and jitter attenuation in a highly integrated PLL solution that eliminates the need for external VCXO and loop filter components The DSPLL loop bandwidth is digitally programmable providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5319 is ideal for providing clock multiplic...

Page 18: ...oop bandwidth is digitally selectable from 150 kHz to 1 3 MHz Operating from a single 1 8 2 5 or 3 3 V supply the Si5322 is ideal for providing low jitter clock multiplication in high performance timing applications See 6 Pin Control Parts Si5316 Si5322 Si5323 Si5365 Si5366 on page 49 for a complete description Figure 3 Si5322 Low Jitter Clock Multiplier Block Diagram Note Not recommended for new ...

Page 19: ...table providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5323 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 6 Pin Control Parts Si5316 Si5322 Si5323 Si5365 Si5366 on page 49 for a complete description Figure 4 Si5323 Jitter Attenuating Clock Multiplier Block Diagra...

Page 20: ... programmable providing jitter performance optimization at the application level The Si5324 features loop bandwidth values as low as 4 Hz Operating from a single 1 8 2 5 or 3 3 V supply the Si5324 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si...

Page 21: ...igitally programmable from 150 kHz to 1 3 MHz Operating from a single 1 8 2 5 or 3 3 V supply the Si5325 is ideal for providing clock multiplication in high performance timing applications See 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 on page 75 for a complete description Figure 6 Si5325 Low Jitter Clock Multiplier Block Diagram Note No...

Page 22: ...width is digitally programmable from 60 Hz to 8 kHz providing jitter performance optimization at the application level Operating from a single 1 8 2 5 or 3 3 V supply the Si5326 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 on page...

Page 23: ...viding jitter performance optimization at the application level The Si5327 features loop bandwidth values as low as 4 Hz Operating from a single 1 8 2 5 or 3 3 V supply the Si5327 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 on pa...

Page 24: ... 3 V supply the Si5365 is ideal for providing clock multiplication in high performance timing applications See 6 Pin Control Parts Si5316 Si5322 Si5323 Si5365 Si5366 on page 49 for a complete description Figure 9 Si5365 Low Jitter Clock Multiplier Block Diagram Note Not recommended for new designs For alternatives see the Si533x family of products C2A CS0_C3A C2B CS1_C4A ALRMOUT C1A CKIN_1 CKIN_1 ...

Page 25: ...from a single 1 8 2 5 or 3 3 V supply the Si5366 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 6 Pin Control Parts Si5316 Si5322 Si5323 Si5365 Si5366 on page 49 for a complete description Figure 10 Si5366 Jitter Attenuating Clock Multiplier Block Diagram C2A CS0_C3A C2B CS1_C4A ALRMOUT C1A CKIN_1 CKIN_1 CKIN_2 CKIN_2 C3B CKIN_3 CKIN_...

Page 26: ...r 3 3 V supply the Si5367 is ideal for providing clock multiplication in high performance timing applications See 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 on page 75 for a complete description Figure 11 Si5367 Clock Multiplier Block Diagram Note Not recommended for new designs For alternatives see the Si53xx family of products C2A CS0_...

Page 27: ...5 or 3 3 V supply the Si5368 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications See 7 Microprocessor Controlled Parts Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 on page 75 for a complete description Figure 12 Si5368 Clock Multiplier and Jitter Attenuator Block Diagram Note Not recommended for new designs For alterna...

Page 28: ...Si5324 and the Si5375 can be viewed as a quad version of the Si5319 However there are not exactly the same This is an overview of the differences 1 The Si5374 75 cannot use a crystal as its OSC reference It requires the use of a single external single ended or differential crystal oscillator 2 The Si5374 75 only supports I2 C as its serial port protocol and does not have SPI No I2 C address pins a...

Page 29: ... the application level The device operates from a single 1 8 or 2 5 V supply with on chip voltage regulators with excellent PSRR The Si5374 is ideal for providing clock multiplication and jitter attenuation in high port count optical line cards requiring independent timing domains Figure 14 Si5374 Functional Block Diagram CKIN3P_B CKOUT3N_B N31 DSPLL B NC1 NC2 CKIN3N_B CKIN4P_B N32 CKIN4N_B Intern...

Page 30: ...or external VCXO and loop filter components Each DSPLL loop bandwidth is digitally programmable from 60 Hz to 8 kHz providing jitter performance optimization at the application level The device operates from a single 1 8 or 2 5 V supply with on chip voltage regulators with excellent PSRR The Si5375 is ideal for providing clock multiplication and jitter attenuation in high port count optical line c...

Page 31: ...mbient Temperature TA 40 25 85 ºC Supply Voltage During Normal Operation VDD 3 3 V Nominal Note 2 Note 2 Note 2 Note 2 2 97 3 3 3 63 V 2 5 V Nominal 2 25 2 5 2 75 V 1 8 V Nominal 1 71 1 8 1 89 V Note 1 All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unle...

Page 32: ... mA Disable Mode 165 mA CKIN_n Input Pins Input Common Mode Voltage Input Threshold Voltage VICM 1 1 8 V 10 0 9 1 4 V 2 5 V 10 1 0 1 7 3 3 V 10 1 1 1 95 Input Resistance CKNRIN Single ended 20 40 60 k Single Ended Input Voltage Swing VISE fCKIN 212 5 MHz See Figure 16 0 2 VPP fCKIN 212 5 MHz See Figure 16 0 25 VPP Differential Input Voltage Swing VID fCKIN 212 5 MHz See Figure 16 0 2 VPP fCKIN 212...

Page 33: ...line to line 500 700 900 mVPP Low swing LVDS 100 load line to line 350 425 500 mVPP Common Mode Output Voltage CKOVCM LVDS 100 load line to line 1 125 1 2 1 275 V Differential Output Resistance CKORD CML LVPECL LVDS Disabled Sleep 170 200 230 Output Voltage Low CKO VOLLH CMOS 0 4 V Output Voltage High CKO VOHLH VDD 1 71 V CMOS 0 8 x VDD V Table 4 DC Characteristics Continued Parameter Symbol Test ...

Page 34: ... 71 V 0 5 V VDD 2 25 V 0 7 V VDD 2 97 V 0 8 V Input Voltage High VIH VDD 1 89 V 1 4 V VDD 2 25 V 1 8 V VDD 3 63 V 2 5 V 3 Level Input Pins Input Voltage Low VILL 0 15 x VDD V Input Voltage Mid VIMM 0 45 x VDD 0 55 x VDD V Input Voltage High VIHH 0 85 x VDD V Input Low Current IILL See note 2 20 µA Table 4 DC Characteristics Continued Parameter Symbol Test Condition Si5316 Si5322 Si5324 Si5325 Si53...

Page 35: ...DD 2 97 V VDD 0 4 V Tri State Leakage Current IOZ RST 0 100 100 µA Table 4 DC Characteristics Continued Parameter Symbol Test Condition Si5316 Si5322 Si5324 Si5325 Si5365 Si5366 Si5367 Si5368 Min Typ Max Units Notes 1 Refer to Section 6 7 1 and 8 2 1 for restrictions on output formats for TQFP devices at 3 3 V 2 This is the amount of leakage that the 3L inputs can tolerate from an external driver ...

Page 36: ...ply to the SDA pin Table 6 SPI Specifications Si5324 Si5325 Si5367 and Si5368 Parameter Symbol Test Conditions Min Typ Max Unit Duty Cycle SCLK tDC SCLK 10 MHz 40 60 Cycle Time SCLK tc 100 ns Rise Time SCLK tr 20 80 25 ns Fall Time SCLK tf 20 80 25 ns Low Time SCLK tlsc 20 20 30 ns High Time SCLK thsc 80 80 30 ns Delay Time SCLK Fall to SDO Active td1 25 ns Delay Time SCLK Fall to SDO Transition t...

Page 37: ...lock Input Pin XA XB with cap to gnd Input Resistance XARIN RATE 1 0 LM ML MH or HM 10 k Input Voltage Level Limits XAVIN 0 1 2 V Input Voltage Swing XAVPP 0 5 1 2 VPP Differential Reference Clock Input Pins XA XB Differential Input Voltage Level Limits XA XBVIN RATE 1 0 LM ML MH or HM 0 1 2 V Input Voltage Swing XAVPP XBVPP 0 5 2 4 VPP SCLK SS SDI th1 td3 SDO td1 td2 tsu1 tr tf tc tsu2 th2 tcs tl...

Page 38: ...Figure 19 Frame Synchronization Timing CLKOUT_2 CLKIN_4 FSYNC_ALIGN FSYNCOUT CLKIN_2 and CLKIN_4 are the active input clock and frame sync pair in this example tFSSU tFSH t 1 fFSYNC Fixed number of CLKOUT_2 clock cycles LATF ...

Page 39: ...ce CKNCIN 3 pF Input Rise Fall Time CKNTRF 20 80 See Figure 17 11 ns CKOUT_n Output Pins See individual data sheets for speed grade limits Output Frequency Output not configured for CMOS or tri state CKOF 19 38 710 MHz 19 43 1049 MHz 0 008 1049 MHz 10 945 MHz 0 002 945 MHz 970 1134 MHz 1 213 1 4 GHz Maximum Output Frequency in CMOS Format CKOFMC 212 5 MHz Output Rise Fall 20 80 at 622 08 MHz CKOTR...

Page 40: ...on of LOSn 100 x N3 570 x N3 TCKIN From last CKIN_n to internal detection of LOSn 0 8 x N3 4 5 x N3 TCKIN From last CKIN_n to internal detection of LOSn N3 1 250 ns 4 5 TCKIN Time to Clear LOL after LOS Cleared tCLRLOL LOS to LOL Assume Fold Fnew Stable XA XB reference 10 ms Table 8 AC Characteristics All Devices Continued Parameter Symbol Test Condition Si5316 Si5322 Si5324 Si5325 Si5365 Si5366 S...

Page 41: ...r 110 110 ps Phase Offset Resolution tOFSTRES using PHASEOFF SETn 7 0 registers N1_HS fVCO Phase Offset Range tOFSTRNG using PHASEOFF SETn 7 0 registers 128 x tOF STRES 127 x tOF STRES PLL Performance Lock Time tLOCKHW RST with valid CKIN to LOL BW 100 Hz 1 2 sec Pin Reset or Register Reset to Microprocessor Access Ready tREADY 10 ms Reset to first on CKOUT tSTART Valid stable clock on CKIN 1 2 se...

Page 42: ...8 Phase Noise fout 622 08 MHz CKOPN 1 kHz Offset 106 dBc Hz 10 kHz Offset 121 dBc Hz 100 kHz Offset 132 dBc Hz 1 MHz Offset 132 dBc Hz Subharmonic Noise SPSUBH Phase Noise 100 kHz Offset 88 76 dBc Spurious Noise SPSPUR 93 70 dBc Table 8 AC Characteristics All Devices Continued Parameter Symbol Test Condition Si5316 Si5322 Si5324 Si5325 Si5365 Si5366 Si5367 Si5368 Min Typ Max Units ...

Page 43: ...Test condition fIN fOUT 622 08 MHz LVPECL clock input 1 19 Vppd with 0 5 ns rise fall time 20 80 LVPECL clock output 2 BWSEL 1 0 loop bandwidth settings provided in Pin Descriptions 3 114 285 MHz 3rd OT crystal used as XA XB input 4 VDD 2 5 V 5 TA 85 C Table 10 Jitter Generation Si5322 Si5325 Si5365 Si5367 Parameter Symbol Test Condition1 2 Min Typ Max Unit Measurement Filter MHz DSPLL Bandwidth2 ...

Page 44: ...l Test Condition Devices Value Unit Thermal Resistance Junction to Ambient JA Still Air Si5316 Si5319 Si5322 Si5323 Si5324 Si5325 32 ºC W Si5365 Si5366 Si5367 Si5368 40 ºC W Thermal Resistance Junction to Case JC Still Air Si5316 Si5319 Si5322 Si5323 Si5324 Si5325 14 ºC W ...

Page 45: ...le and consistent operation over process temperature and voltage variations A simplified block diagram of the DSPLL is shown in Figure 20 This algorithm processes the phase detector error term and generates a digital frequency control word M to adjust the frequency of the digitally controlled oscillator DCO The narrowband configuration devices Si5316 Si5319 Si5323 Si5324 Si5326 Si5327 Si5366 Si536...

Page 46: ...26 Si5327 Si5367 Si5368 and Si5369 provide a programmable range of clock multiplications To assist users in finding valid divider settings for a particular input frequency and clock multiplication ratio Silicon Laboratories offers PC based software DSPLLsim that calculates these settings automatically When multiple divider combinations produce the same output frequency the software recommends the ...

Page 47: ...nal jitter for a specified jitter frequency The jitter transfer characteristic determines the amount of input clock jitter that passes to the outputs The DSPLL technology used in the Any Frequency Precision Clock devices provides tightly controlled jitter transfer curves because the PLL gain parameters are determined largely by digital circuits which do not vary over supply voltage process and tem...

Page 48: ...e versus input jitter frequency For jitter frequencies above the loop bandwidth the tolerance is a constant value Aj0 Beginning at the PLL bandwidth the tolerance increases at a rate of 20 dB decade for lower input jitter frequencies Figure 23 Jitter Tolerance Mask Template The equation for the high frequency jitter tolerance can be expressed as a function of the PLL loop bandwidth i e bandwidth F...

Page 49: ...tandard SONET and data communications frequency scaling including simple integer frequency multiplication to fractional settings required for coding and decoding 6 1 1 Clock Multiplication Si5316 The device accepts dual input clocks in the 19 39 78 155 311 or 622 MHz frequency range and generates a de jittered output clock at the same frequency The frequency range is set by the FRQSEL 1 0 pins as ...

Page 50: ...st be equal and are set by the FRQSEL 1 0 pins Input divider settings are controlled by the CK1DIV and CK2DIV pins as shown in Table 14 Figure 24 Si5316 Divisor Ratios Table 14 Input Divider Settings CKnDIV N3n Input Divider L 1 M 4 H 32 Table 15 Si5316 Bandwidth Values FRQSEL 1 0 Nominal Frequency Values MHz LL LM LH ML MM MH BW 1 0 19 44 MHz 38 88 MHz 77 76 MHz 155 52 MHz 311 04 MHz 622 08 MHz H...

Page 51: ...the Si5322 and Si5365 2 The listed output frequencies appear on CKOUTn For the Si5365 and Si5366 sub multiples are available on CKOUT3 and CKOUT4 using the DIV34 1 0 control pins 3 All ratios are exact but the frequency values are rounded 4 For bandwidth settings f3 values and frequency operating ranges consult DSPLLsim 5 For the Si5366 with CK_CONF 1 CKIN3 and CKIN4 are the same frequency as FS_O...

Page 52: ...HH 32 x 255 237 669 33 669 33 NA 18 LHLL 32 x 255 236 672 16 672 16 NA 19 LHLM 48 933 12 933 12 0 008 20 LHLH 54 1049 76 1049 76 0 008 21 LHML 38 88 1 38 88 38 88 0 008 22 LHMM 2 77 76 77 76 0 008 23 LHMH 4 155 52 155 52 0 008 24 LHHL 16 622 08 622 08 0 008 25 LHHM 16 x 255 238 666 51 666 51 NA 26 LHHH 16 x 255 237 669 33 669 33 NA 27 MLLL 16 x 255 236 672 16 672 16 NA Table 16 SONET Clock Multipl...

Page 53: ...MMH 1 4 38 88 38 88 0 008 42 MMHL 1 2 77 76 77 76 0 008 43 MMHM 1 155 52 155 52 0 008 44 MMHH 255 238 166 63 166 63 NA 45 MHLL 255 237 167 33 167 33 NA 46 MHLM 255 236 168 04 168 04 NA 47 MHLH 2 311 04 311 04 0 008 48 MHML 4 622 08 622 08 0 008 49 MHMM 4 x 255 238 666 51 666 51 NA 50 MHMH 4 x 255 237 669 33 669 33 NA 51 MHHL 4 x 255 236 672 16 672 16 NA 52 MHHM 166 63 238 255 155 52 155 52 NA 53 M...

Page 54: ... 255 236 672 16 672 16 NA 69 HMLL 622 08 1 32 19 44 19 44 0 008 70 HMLM 1 16 38 88 38 88 0 008 71 HMLH 1 8 77 76 77 76 0 008 72 HMML 1 4 155 52 155 52 0 008 73 HMMM 1 2 311 04 311 04 0 008 74 HMMH 1 622 08 622 08 0 008 75 HMHL 255 238 666 51 666 51 NA 76 HMHM 255 237 669 33 669 33 NA 77 HMHH 255 236 672 16 672 16 NA 78 HHLL 666 51 1 4 x 238 255 155 52 155 52 NA 79 HMML 1 4 166 63 166 63 NA 80 HHLM...

Page 55: ... 1 669 33 669 33 NA 86 HHMM 672 16 1 4 x 236 255 155 52 155 52 NA 87 HMML 1 4 168 04 168 04 NA 88 HHMH 236 255 622 08 622 08 NA 89 HMMH 1 672 16 672 16 NA Table 16 SONET Clock Multiplication Settings FRQTBL L Continued No FRQSEL 3 0 WB fIN MHz Mult Factor Nominal fOUT MHz All Devices Si5366 Only fCKOUT5 MHz CK_CONF 0 FS_OUT MHz CK_CONF 1 ...

Page 56: ... LMLH 51 8 x 66 64 x 255 237 176 84 12 LMML 17 2 212 5 13 LMMM 17 425 14 LMMH 25 x 66 64 644 53 15 LMHL 51 2 x 66 64 657 42 16 LMHM 25 x 66 64 x 255 238 690 57 17 LMHH 25 x 66 64 x 255 237 693 48 18 LHLL 51 2 x 66 64 x 255 238 704 38 19 LHLM 51 2 x 66 64 x 255 237 707 35 20 LHLH 31 25 2 62 5 21 LHML 4 125 22 LHMM 8 250 23 LHMH 53 125 2 106 25 24 LHHL 4 212 5 25 LHHM 8 425 26 LHHH 106 25 3 2 x 66 6...

Page 57: ...6 64 x 255 237 176 84 49 MMHM 4 x 66 64 657 4 50 MMHH 4 x 66 64 x 255 238 704 38 51 MHLL 4 x 66 64 x 255 237 707 35 52 MHLM 161 13 4 5 x 64 66 125 53 MHLH 255 238 172 64 54 MHML 255 237 173 37 55 MHMM 4 644 53 56 MHMH 4 x 255 238 690 57 57 MHHL 4 x 255 237 693 48 58 MHHM 164 36 2 3 x 64 66 106 25 59 MHLH 255 238 176 1 60 MHML 255 237 176 84 61 MHMM 4 657 42 62 MHMH 4 x 255 238 704 38 63 MHHL 4 x 2...

Page 58: ...2 HLHL 4 x 237 255 657 42 83 MHMM 4 707 35 84 HMLL 212 5 2 425 85 HMLM 425 1 425 86 HMLH 644 53 1 5 x 64 66 125 87 HMML 1 4 161 13 88 HMMM 1 644 53 89 HMMH 255 238 690 57 90 HMHL 255 237 693 48 91 HMHM 657 42 1 6 x 64 66 106 25 92 HMML 1 4 164 36 93 HMMM 1 657 42 94 HMMH 255 238 704 38 95 HMHL 255 237 707 35 96 HMHH 690 57 1 5 x 64 66 x 238 255 125 97 HHLL 1 4 x 64 66 x 238 255 156 25 98 HHLM 1 4 ...

Page 59: ... 25 109 HHLL 1 4 x 64 66 x 238 255 159 375 110 HHLM 1 4 x 238 255 164 36 111 HMML 1 4 176 1 112 HHLH 238 255 657 42 113 HMMM 1 704 38 114 HHHH 707 35 1 6 x 64 66 x 237 255 106 25 115 HHMM 1 4 x 64 66 x 237 255 159 375 116 HHMH 1 4 x 237 255 164 36 117 HMML 1 4 176 84 118 HHHL 237 255 657 42 119 HMMM 1 707 35 Table 17 Datacom Clock Multiplication Settings FRQTBL M CK_CONF 0 Continued Setting FRQSEL...

Page 60: ...1 LMLH 10625 3888 53 125 12 LMML 3125 972 62 5 13 LMMM 10625 1944 106 25 14 LMMH 3125 486 125 15 LMHL 15625 1944 156 25 16 LMHM 31875 3888 159 375 17 LMHH 15625 1944 x 66 64 161 13 18 LHLL 31875 3888 x 66 64 164 36 19 LHLM 15625 1944 x 66 64 x 255 238 172 64 20 LHLH 31875 3888 x 66 64 x 255 238 176 1 21 LHML 10625 972 212 5 22 LHMM 10625 486 425 23 LHMH 15625 486 x 66 64 644 53 24 LHHL 31875 972 x...

Page 61: ...875 15552 159 375 42 MMHL 15625 7776 x 66 64 161 13 43 MMHM 31875 15552 x 66 64 164 36 44 MMHH 15625 7776 x 66 64 x 255 238 172 64 45 MHLL 31875 15552 x 66 64 x 255 238 176 1 46 MHLM 10625 3888 212 5 47 MHLH 10625 1944 425 48 MHML 15625 1944 x 66 64 644 53 49 MHMM 31875 3888 x 66 64 657 42 50 MHMH 15625 1944 x 66 64 x 255 238 690 57 51 MHHL 31875 3888 x 66 64 x 255 238 704 38 Table 18 SONET to Dat...

Page 62: ...2 5 59 HLMH 10625 3888 425 60 HLHL 15625 3888 x 66 64 644 53 61 HLHM 31875 7776 x 66 64 657 42 62 HLHH 15625 3888 x 66 64 x 255 238 690 57 63 HMLL 31875 7776 x 66 64 x 255 238 704 38 64 HMLM 622 080 15625 15552 x 66 64 644 53 65 HMLH 31875 31104 x 66 64 657 42 66 HMML 15625 15552 x 66 64 x 255 238 690 57 67 HMMM 31875 31104 x 66 64 x 255 238 704 38 Table 18 SONET to Datacom Clock Multiplication Se...

Page 63: ...e reference input because it is a fixed frequency reference and is only used as a jitter reference and holdover reference see 6 4 Digital Hold VCO Freeze on page 69 However care must be taken in certain areas for optimum performance For details on this subject refer to Appendix B Frequency Plans and Jitter Performance Si5316 Si5319 Si5323 Si5324 Si5326 Si5327 Si5366 Si5368 Si5369 Si5374 Si5375 on ...

Page 64: ...ill wait until they appear at which time the calibration will start All outputs are on during the calibration process After a successful self calibration has been performed with a valid input clock no subsequent self calibrations are performed unless one of the above conditions are met If the input clock is lost following self calibration the device enters digital hold mode When the input clock re...

Page 65: ...FRQSEL3 FRQSEL3 Yes 30 SFOUT1 N A SFOUT1 No but skew not guaranteed without Reset 33 SFOUT0 N A SFOUT0 No but skew not guaranteed without Reset Table 21 Si5365 and Si5366 Pins and Reset Pin Si5365 Pin Name Si5366 Pin Name Must Reset after Changing 4 FRQTBL FRQTBL Yes 32 N A RATE 0 Yes 42 N A RATE 1 Yes 51 N A CK_CONF Yes 54 N A DEC No 55 N A INC No 60 BWSEL0 BSWEL0 Yes 61 BWSEL1 BWSEL1 Yes 66 DIV3...

Page 66: ..._CONF 0 any of the four input clocks may be selected manually however when CK_CONF 1 the inputs are paired CKIN1 is paired with CKIN3 and likewise for CKIN2 and CKIN4 Therefore only two settings are available to select one of the two pairs Notes 1 To avoid clock switching based on intermediate states during a CS state change the CS input pins are internally deglitched 2 If the selected clock enter...

Page 67: ...ritization of clock inputs for automatic switching is shown in Table 27 and Table 28 This priority is hardwired in the devices Table 24 Automatic Manual Clock Selection AUTOSEL Clock Selection Mode L Manual See Previous Section M Automatic Non revertive H Automatic Revertive Table 25 Clock Active Indicators AUTOSEL M or H Si5322 and Si5323 CS_CA Active Clock 0 CKIN1 1 CKIN2 Table 26 Clock Active I...

Page 68: ... transients to the clock outputs during input clock switching All switching between input clocks occurs within the input multiplexor and phase detector circuitry The phase detector circuitry continually monitors the phase difference between each input clock and the DSPLL output clock fOSC The phase detector circuitry can lock to a clock signal at a specified phase offset relative to fOSC so that t...

Page 69: ...l 6 4 2 Recovery from Digital Hold Si5316 Si5323 Si5366 When the input clock signal returns the device transitions from digital hold to the selected input clock The device performs hitless recovery from digital hold The clock transition from digital hold to the returned input clock includes phase buildout to absorb the phase difference between the digital hold clock phase and the input clock phase...

Page 70: ...ween each FS_OUT cycle At power up or any time after the PLL has lost lock and relocked the device automatically performs a realignment of FS_OUT using the currently active sync input After this as long as the PLL remains in lock and a realignment is not requested FS_OUT will include a fixed number of high speed clock cycles even if input clock switches are performed If many clock switches are per...

Page 71: ...Output Clock Drivers The SFOUT 1 0 pins can also be used to disable the output Disabling the output puts the CKOUT and CKOUT pins in a high impedance state relative to VDD common mode tri state while the two outputs remain connected to each other through a 200 on chip resistance differential impedance of 200 The maximum amount of internal circuitry is powered down minimizing power consumption and ...

Page 72: ...lidation time then the alarm remains asserted and the validation time starts over 6 9 1 1 Narrowband LOS Algorithm Si5316 Si5323 Si5366 The LOS circuitry divides down each input clock to produce an 8 kHz to 2 MHz signal For the Si5316 the output of divider N3 See Figure 1 is used The LOS circuitry over samples this divided down input clock using a 40 MHz clock to search for extended periods of tim...

Page 73: ...l alarm indicators are used in determining the output alarms LOSn_INT See section 6 9 1 Loss of Signal Alarms Si5316 Si5322 Si5323 Si5365 Si5366 for a description of how LOSn_INT is determined FOSn_INT See section 6 9 2 FOS Alarms Si5365 and Si5366 for a description of how FOSn_INT is determined ALIGN_INT See section 6 9 3 FSYNC Align Alarm Si5366 and CK_CONF 1 and FRQTBL L for a description of ho...

Page 74: ...22 Si5365 A PLL loss of lock indicator is not available for these devices 6 10 Device Reset Upon powerup the device internally executes a power on reset POR which resets the internal device logic The pin RST can also be used to initiate a reset The device stays in this state until a valid CKINn is present when it then performs a PLL Self Calibration See 6 2 PLL Self Calibration 6 11 DSPLLsim Confi...

Page 75: ...ends the divider settings that yield the best combination of phase noise performance and power consumption 7 1 1 Jitter Tolerance Si5319 Si5324 Si5325 Si5326 Si5327 Si5368 Si5369 Si5374 and Si5375 See Section 5 2 3 7 1 2 Wideband Parts Si5325 Si5367 These devices operate as wideband clock multipliers without an external resonator or reference clock This mode may be desirable if the input clock is ...

Page 76: ...upport either a crystal oscillator or an input buffer single ended or differential so that an external oscillator can become the reference source In both cases there are wide margins in the absolute frequency of the reference input because it is a fixed frequency and is used only as a jitter reference and holdover reference see 7 6 Digital Hold on page 86 See Appendix A Narrowband References on pa...

Page 77: ... 20 N2 N2 N2_HS x N2_LS N2_HS 1 N2_LS 32 34 36 2 9 N2_HS 4 5 11 N2_LS 2 4 6 2 20 N3 N3 N3n N3n 1 2 3 2 19 N3n 1 2 3 2 19 CKIN_1 CKIN_1 CKIN_2 CKIN_2 CKIN_3 CKIN_3 CKIN_4 CKIN_4 CKOUT_1 CKOUT_1 NC1 1 0 CKOUT_2 CKOUT_2 NC2 1 0 CKOUT_3 CKOUT_3 NC3 1 0 CKOUT_4 CKOUT_4 NC4 1 0 2 2 2 2 2 2 2 2 DCO fOSC Xtal or Refclock Si5319 Si5324 Si5326 Si5327 Si5368 Si5369 Refclock only for the Si5374 and Si5375 fx ...

Page 78: ... the loop BW and its effect on jitter attenuation see Appendix H Jitter Attenuation and Loop BW on page 164 7 1 4 1 Low Loop Bandwidth Si5324 Si5327 Si5369 Si5374 The loop BW of the Si5324 Si5327 Si5369 and Si5374 is significantly lower than the BW of the Si5326 The available Si5324 27 69 74 loop bandwidth settings and their register control values for a given frequency plan are listed by DSPLLsim...

Page 79: ... is the LSB of register 137 When FAST_LOCK is high the lock time decreases Because the Si5324 27 64 74 is initialized with FAST_LOCK low it must be written before ICAL Typical Si5324 69 74 lock time as defined from the start of ICAL until LOL goes low with FASTLOCK set is from one to ten seconds The Si5327 lock time can be as long as 20 seconds To reduce lock times it is recommended that a value o...

Page 80: ...er in frequency by more than 100 ppm Figure 27 Si5324 Si5325 Si5326 Si5327 and Si5374 Input Clock Selection 44 1 1 CKOUT always ON including during an ICAL Use these settings to preserve output to output skew Notes 1 Case 1 should be selected when an output clock is not desired until the part has been initialized after power up but is desired all of the time after initialization 2 Case 2 should be...

Page 81: ...N1 CKIN3 01 CKIN2 CKIN2 CKIN4 10 CKIN3 Not used 11 CKIN4 Not used Note Setting the CKSEL_PIN register bit to one allows the CS 1 0 pins to continue to control input clock selection If CS_PIN is set to zero the CKSEL_REG 1 0 register bits perform the input clock selection function CKIN1 CKIN2 CKIN3 CKIN4 Clock priority logic CK_PRIORn 0 1 CKSEL_REG AUTOSEL_REG 0 1 CKSEL_PIN LOS FOS detect LOS FOS d...

Page 82: ...bits as shown in the Si5325 Si5326 and Si5374 For the default priority arrangement automatic switching mode selects CKIN1 at powerup reset or when in revertive mode with no alarms present on CKIN1 If an alarm condition occurs on CKIN1 and there are no active alarms on CKIN2 then the device switches to CKIN2 If both CKIN1 and CKIN2 are alarmed then the device enters digital hold mode If automatic m...

Page 83: ...ion choices In non revertive mode once CKIN2 is selected CKIN2 selection remains as long as it is valid even if alarms are cleared on CKIN1 7 4 3 Hitless Switching with Phase Build Out Si5324 Si5326 Si5327 Si5368 Si5369 Si5374 Silicon Laboratories switching technology performs phase build out which maintains the phase of the output when the input clock is switched This minimizes the propagation of...

Page 84: ...d the part will Initially lock to either the XA XB OSC_P and OSC_N for the Si5374 75 or to CKIN1 Automatically select CKIN1 if it is available Automatically and hitlessly switch to XA XB if CKIN1 fails Automatically and hitlessly switch back to CKIN1 when it subsequently returns For the Si5319 Clock selection is manual using an input pin Clock switching is not hitless CKIN2 is not available 7 5 2 ...

Page 85: ...very low drift a TCXO or OCXO reference is necessary CKOUT Jitter XA XB to CKOUT jitter transfer function is roughly one to one For very low jitter either use a high quality crystal or external oscillator 3rd overtone crystals have lower close in phase noise In general higher XA XB frequency lower jitter XA XB frequency accuracy For hitless switching to meet all published specifications the XA XB ...

Page 86: ... is validated Upon entering digital hold the internal DCO is initially held to its last frequency value M See Figure 30 Next the DCO slowly transitions to a historical average frequency value supplied to the DSPLL MHIST as shown in Figure 30 Values of M starting from time t HIST_DEL HIST_AVG and ending at t HIST_DEL are averaged to compute MHIST This historical average frequency value is taken fro...

Page 87: ...2 10101 210 00110 0 0064 10110 419 00111 0 01 10111 839 01000 0 03 11000 1678 01001 0 05 11001 3355 01010 0 10 11010 6711 01011 0 20 11011 13422 01100 0 41 11100 26844 01101 0 82 11101 53687 01110 1 64 11110 107374 01111 3 28 11111 214748 Table 43 Digital Hold History Averaging Time HIST_AVG 4 0 History Averaging Time ms HIST_AVG 4 0 History Averaging Time ms 00000 0 0000 10000 26 00001 0 0004 100...

Page 88: ...table output frequency until the input clock returns and is validated When the device enters digital hold the internal oscillator is initially held to the frequency value at roughly one second prior to the leading edge of the alarm condition VCO freeze is not compliant with SONET SDH MTIE requirements applications requiring SONET SDH MTIE requirements should use the Si5324 Si5326 Si5368 Si5369 or ...

Page 89: ...requency only phase increments are allowed and negative settings in the CLAT register or attempts to decrement the phase via writes to the CLAT register will be ignored Because of this restriction when there is a choice between using N1_HS 4 and another N1_HS value that can produce the desired multiplication ratio the other N1_HS value should be selected This restriction also applies when using th...

Page 90: ...ut clock output to output delays can easily be set 7 7 4 Output to output Skew Si5324 Si5326 Si5327 Si5368 Si5369 Si5374 The output to output skew is guaranteed to be preserved only if the following two register bits are both high Register Bit Location CKOUT_ALWAYS_ON addr 0 bit 5 SQICAL addr 3 bit 4 In addition if SFOUT is changed the output to output skew may be disturbed until after a successfu...

Page 91: ...1 4 8 2 010 8 16 4 011 16 32 8 100 32 64 16 101 64 128 32 110 128 256 64 111 256 512 128 CKIN3 CKIN4 CLKIN3RATE Clock select DCO 4 85 GHz to 5 67 GHz CKOUT2 N1_HS NC2_LS NC5_LS FS_OUT CLKIN4RATE to align Typically the same frequency CKIN3 CKIN4 CLKIN3RATE Clock select DCO 4 85 GHz to 5 67 GHz N1_HS NC2_LS NC5_LS CLKIN4RATE to align Typically the same frequency ...

Page 92: ... is not requested FS_OUT will include a fixed number of high speed clock cycles even if input clock switches are performed If many clock switches are performed in phase build out mode it is possible that the input sync to output sync phase relationship will shift due to the accumulated residual phase transients of the phase build out circuitry The ALIGN_ERR 8 0 status register reports the deviatio...

Page 93: ...1 and CKIN2 can also be included in the state machine decision making as described in Section 7 11 Alarms Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 however in frame sync mode CK_CONFIG_REG 1 the FOS alarms for CKIN3 and CKIN4 are ignored 7 8 4 FS_OUT Polarity and Pulse Width Control Si5368 Additional output controls are available for FS_OUT The active polarity of FS_OUT...

Page 94: ...the differential signal to remain at its high logic level while the negative output remains at the low logic level For CMOS output buffer format both outputs remain high during the Hold Logic 1 state These functions are controlled by the HLOG_n bits When entering or exiting the Hold Logic 1 or Hold Logic 0 states no glitches or runt pulses are generated on the outputs Changes to SFOUT or HLOG will...

Page 95: ...lable settings Note that only for VALTIME 1 0 00 hitless switching is not possible 7 11 1 Loss of Signal Alarms Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 The device has loss of signal circuitry that continuously monitors CKINn for missing pulses The LOS circuitry generates an internal LOSn_INT output signal that is processed with other alarms to generate CnB and ALARMOU...

Page 96: ...FOS or by setting DHOLD register 3 bit 5 7 11 1 5 Wideband LOS Algorithm Si5322 Si5365 Each input clock is divided down to produce a 78 kHz to 1 2 MHz signal before entering the LOS monitoring circuitry The same LOS algorithm as described in the above section is then used FOS is not available in wideband devices 7 11 1 6 LOS Alarm Outputs Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5369 Si5374 Si5...

Page 97: ... clocks as shown in Table 51 When the FOS reference is the XA XB oscillator either internal or external the value of Q in Figure 33 is always 2 for an effective CLKINnRATE of 1 as shown in Table 51 For example to monitor a 544 MHz clock at CKIN1 with a FOS reference of 34 MHz at CKIN2 CLK1RATE 5 CLK2RATE 1 FOSREFSEL 2 0 010 Table 50 FOS Reference Clock Selection FOS Reference FOSREFSEL 2 0 Si5326 ...

Page 98: ...puts is a function of the input clock configuration and the frequency offset alarm enable as shown in Table 52 The LOSn_INT and FOSn_INT signals are the raw outputs of the alarm monitors These appear directly in the device status registers Sticky versions of these bits LOSn_FLG FOSn_FLG drive the output interrupt and can be individually masked When the device inputs are configured as four input cl...

Page 99: ...326 Si5327 Si5368 Si5369 Si5374 Si5375 The reference clock input on the XA XB port is monitored for LOS The LOS circuitry divides the signal at XA XB by 128 producing a 78 kHz to 1 2 MHz signal and monitors the signal for LOS using the same algorithm as described in Section 7 11 1 Loss of Signal Alarms Si5319 Si5324 Si5325 Si5326 Si5327 Si5367 Si5368 Si5369 Si5374 Si5375 The LOSX_INT read only bit...

Page 100: ...ag 7 12 Device Reset Upon powerup or asserting Reset via the RST pin or software the device internally executes a power on reset POR which resets the internal device logic and tristates the device outputs The device waits for configuration commands and the receipt of the ICAL 1 command to start its calibration Any changes to the CMODE pin require that RST be toggled to reset the part The power up ...

Page 101: ...ifications and timing diagram for the I2C bus can be found in the I2C Bus Specification standard fast mode operation See http www standardics nxp com literature books i2c pdf i2c bus specification pdf The maximum I2C clock speed is 400 kHz Figure 34 I2 C Command Format In Figure 35 the value 68 is seven bits The sequence of the example is Write register 00 with the value 0xAA then read register 00...

Page 102: ... one byte of data from the device and the Read Address Increment reads one byte and increments the register address automatically The second byte of the pair is the address or data byte As shown in Figure 36 and Figure 37 SSb should be held low during the entire two byte transfer Raising SSb resets the internal state machine so SSb can optionally be raised between each two byte transfers to guaran...

Page 103: ...n of the registers 7 16 DSPLLsim Configuration Software To simplify frequency planning loop bandwidth selection and general device configuration of the Any Frequency Precision Clocks Silicon Laboratories has a configuration utility DSPLLsim for the Si5319 Si5325 Si5326 Si5327 Si5367 Si5368 and Si5369 For the Si5374 and Si5375 there is a different configuration utility Si537xDSPLLsim Both are avail...

Page 104: ...its in Table 8 AC Characteristics All Devices AC coupling the input clocks is recommended because it removes any issue with common mode input voltages However either ac or dc coupling is acceptable Figures 38 and 39 show various examples of different input termination arrangements Unused inputs should have an ac ground connection For microprocessor controlled devices the PD_CKn bits may be set to ...

Page 105: ...le R3 150 ohms C1 100 nF R4 150 ohms C2 100 nF VICM CKIN CKIN R5 40 kohm R6 40 kohm VDD R2 Notes 3 3 V 100 ohm Locate R1 near CMOS driver 2 5 V 49 9 ohm Locate other components near Si5317 1 8 V 14 7 ohm Recalculate resistor values for other drive strengths Additional Notes 1 Attenuation circuit limits overshoot and undershoot 2 Use only with 50 duty cycle clock signals 3 Assumes the CMOS output c...

Page 106: ...ifth output must be disabled When Vdd 3 3 V and there are five enabled outputs there can be no more than three outputs that are either LVPECL or CMOS All other configurations are valid including those with Vdd 2 5 V 8 2 2 Typical Output Circuits It is recommended that the outputs be ac coupled to avoid common mode issues This suggestion does not apply to the Si5366 and Si5368 when CKOUT5 is config...

Page 107: ... pin controlled parts have a DBL2_BY pin that can be used to disable CKOUT2 Table 57 Disabling Unused Output Driver Output Driver Si5365 Si5366 Si5325 Si5326 Si5367 Si5368 CKOUT1 and CKOUT2 N A Use SFOUT_REG to disable individ ual CKOUTn CKOUT3 and CKOUT4 DBL34 CKOUT5 FS_OUT DBL5 DBL_FS Si53xx Rcvr 10 10 80 All resistors are located next to RCVR Si53xx CMOS Logic CKOUTn Optionally Tie CKOUTn Outpu...

Page 108: ...pk Vocm Reserved HH LVDS HM 7 35 7 1 2 CML HLK 6 25 5 3 05 LVPECL MH 5 75 1 5 2 10 Reserved MM 4 Low Swing LVDS ML 3 25 5 1 2 CMOS LH 2 3 3 1 65 Disable LM 1 Reserved LL 0 Notes 1 Typical measurements with an Si5326 at VC 3 3 V 2 For all measurements Vpk pk on a single output double the values for differential Vdd 3 3 V 50 ac load to ground Output Disable 100 100 CKOUT CKOUT ...

Page 109: ...Si53xx RM Rev 0 52 109 8 3 Typical Scope Shots for SFOUT Options Figure 46 sfout_2 CMOS Figure 47 sfout_3 lowSwingLVDS ...

Page 110: ...Si53xx RM 110 Rev 0 52 Figure 48 sfout_5 LVPECL Figure 49 sfout_6 CML ...

Page 111: ...Si53xx RM Rev 0 52 111 Figure 50 sfout_7 LVDS ...

Page 112: ... the crystal be covered with some type of thermal cap For various crystal vendors and part numbers see Appendix A Narrowband References on page 118 1 For SONET applications the best jitter performance is with a 114 285 MHz third overtone crystal The Si5327 crystal is fundamental mode and is limited to values between 37 MHz and 41 MHz 2 The jitter transfer for the external reference to CKOUT is nea...

Page 113: ...e Input Example Not for Si5374 or Si5375 Figure 54 Differential OSC Reference Input Example for Si5374 and Si5375 LVDS LVPECL CML etc 0 01 F 1 2 V 0 6 V Si53xx XA XB 10 k 100 0 01 F 10 k LVDS LVPECL CML etc 0 01 F 1 2 V 0 6 V Si5374 75 OSC P OSC N 100 0 01 F 2 5 k ...

Page 114: ...t Voltage Low Vill 15 x VDD Input Voltage Mid Vimm 45 x Vdd 55 x VDD Input Voltage High Vihh 85 x Vdd Input Low Current Iill 6 µA Input Mid Current Iimm 2 µA 2 µA Input High Current Iihh 6 µA Note The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver External Driver Si53xx Iimm 75 k VDD 75 k ...

Page 115: ... the listed currents If a pin is tied to ground or Vdd no resistors are needed If a pin is left open no connect no resistors are needed Parameter Symbol Min Max Input Low Current Iill 30 µA Input Mid Current Iimm 11 µA 11 µA Input High Current Iihh 30 µA Note The above currents are the amount of leakage that the 3L inputs can tolerate from an external driver External Driver Si53xx Iimm 18 k VDD 18...

Page 116: ... 58 shows a typical power supply bypass network for QFN In both cases the center ground pad under the device must be electrically and thermally connected to the ground plane Figure 57 Typical Power Supply Bypass Network TQFP Package Figure 58 Typical Power Supply Bypass Network QFN Package TQFP PKG VDD GND C1 C8 C9 Ferrite Bead System Power Supply 1 8 2 5 or 3 3 V 0 1 uF 1 0 uF Ferrite bead is Ven...

Page 117: ...Si53xx RM Rev 0 52 117 10 Packages and Ordering Guide Refer to the respective data sheet for your device packaging and ordering information ...

Page 118: ... ndk com en 20 ppm 20 ppm Pericom Saronix eCera FLB420001 http www pericom com saronix http www ecera tw 100 ppm 100 ppm Siward XTL573200NLG 114 285 MHz OR http www siward com 20 ppm 20 ppm TXC 7MA1400014 http www txc com tw 100 ppm 100 ppm Vectron VXM7 1074 114M285000 http www vectron com 100 ppm 100 ppm Note See the manufacturer s data sheets for detailed specifications for each crystal Table 60...

Page 119: ...l mode crystals that are in this range For a more detailed discussion of the trade offs associated with this approach and a list of approved low frequency crystals please see the application note AN591 which can be downloaded from www silabs com timing Reference Drift During Digital Hold long term and temperature related drift of the reference input result in a one to one drift of the output frequ...

Page 120: ...Si53xx RM 120 Rev 0 52 Figure 59 Typical Reference Jitter Transfer Function 38 88MHz XO 38 88MHz CKIN 38 88MHz CKOUT 30 20 10 0 10 1 10 100 1000 10000 100000 1000000 Frequency Hz Power dB Jitter Xfer ...

Page 121: ...n f3 and a PLL multiplier ratio that is comprised of large and mutually prime nominators and denominators Specifically for CKOUT CKIN x P Q if P and Q are mutually prime and large in size then f3 may have a low value Very low values of f3 usually result in extra jitter as can be seen in Figures 60 through 62 and in Table 61 For the f3 study the input output and VCO frequencies were held constant w...

Page 122: ... allow an FPGA s output to be used to produce a very clean clock as can be seen from the jitter numbers below Figure 61 Jitter vs f3 with FPGA Table 61 Jitter Values for Figure 61 f3 3 214 kHz f3 16 1 kHz CKIN 38 88 MHz CKIN 194 4 MHz Jitter Bandwidth Jitter RMS Jitter RMS OC 48 12 kHz to 20 MHz 1 034 fs 285 fs OC 192 20 kHz to 80 MHz 668 fs 300 fs OC 192 4 MHz to 80 MHz 169 fs 168 fs OC 192 50 kH...

Page 123: ...gure 62 Reference vs Output Frequency The crystal frequency of 114 285 MHz was picked for its lack of integer relationship to most of the expected output frequencies If for instance an output frequency of 457 14 MHz 4 x 114 285 MHz were desired it would be preferable not to use the 114 285 MHz crystal as the reference For a more detailed study of this see Appendix G Near Integer Ratios on page 162...

Page 124: ...iscussion of the available reference frequencies see section Resonator External Clock Selection on page 118 Figure 63 622 08 MHz Output with a 114 285 MHz Crystal Jitter Band Jitter RMS SONET_OC48 12 kHz to 20 MHz 242 fs SONET_OC192_A 20 kHz to 80 MHz 269 fs SONET_OC192_B 4 to 80 MHz 166 fs SONET_OC192_C 50 kHz to 80 MHz 265 fs Brick Wall_800 Hz to 80 MHz 270 fs Note Jitter integration bands inclu...

Page 125: ...S SONET_OC48 12 kHz to 20 MHz 379 fs SONET_OC192_A 20 kHz to 80 MHz 376 fs SONET_OC192_B 4 to 80 MHz 132 fs SONET_OC192_C 50 kHz to 80 MHz 359 fs Brick Wall_800 Hz to 80 MHz 385 fs Note Jitter integration bands include low pass 20 dB Dec and hi pass 60 dB Dec roll offs per Telcordia GR 253 CORE ...

Page 126: ...xcept as noted the Any Frequency part was an Si5326 operating at 3 3 V with an ac coupled differential PECL output and an ac coupled differential sine wave input from the RF generator at 0 dBm Note that as with any PLL the output jitter that is below the loop bandwidth of the Any Frequency device is caused by the jitter of the input clock not the Any Frequency Precision Clock Except as noted the l...

Page 127: ...Si53xx RM Rev 0 52 127 Figure 66 155 52 MHz In 622 08 MHz Out Loop BW 7 Hz Si5324 ...

Page 128: ...Si53xx RM 128 Rev 0 52 Figure 67 19 44 MHz In 156 25 MHz Out Loop BW 80 Hz ...

Page 129: ...Si53xx RM Rev 0 52 129 Figure 68 19 44 MHz In 156 25 MHz Out Loop BW 5 Hz Si5324 ...

Page 130: ...Si53xx RM 130 Rev 0 52 Figure 69 27 MHz In 148 35 MHz Out Light Trace BW 6 Hz Dark Trace BW 110 Hz Si5324 ...

Page 131: ...Si53xx RM Rev 0 52 131 Figure 70 61 44 MHz In 491 52 MHz Out Loop BW 7 Hz Si5324 ...

Page 132: ...Si53xx RM 132 Rev 0 52 Figure 71 622 08 MHz In 672 16 MHz Out Loop BW 6 9 kHz ...

Page 133: ...Si53xx RM Rev 0 52 133 Figure 72 622 08 MHz In 672 16 MHz Out Loop BW 100 Hz ...

Page 134: ...Si53xx RM 134 Rev 0 52 Figure 73 156 25 MHz In 155 52 MHz Out ...

Page 135: ...Table 63 Jitter Values for Figure 74 Jitter Bandwidth 644 531 MHz Jitter RMS Broadband 1 kHz to 10 MHz 223 fs OC 48 12 kHz to 20 MHz 246 fs OC 192 20 kHz to 80 MHz 244 fs OC 192 4 MHz to 80 MHz 120 fs OC 192 50 kHz to 80 MHz 234 fs Broadband 800 Hz to 80 MHz 248 fs ...

Page 136: ...Table 64 Jitter Values for Figure 75 Jitter Bandwidth 690 569 MHz Jitter RMS Broadband 1 kHz to 10 MHz 244 fs OC 48 12 kHz to 20 MHz 260 fs OC 192 20 kHz to 80 MHz 261 fs OC 192 4 MHz to 80 MHz 120 fs OC 192 50 kHz to 80 MHz 253 fs Broadband 800 Hz to 80 MHz 266 fs ...

Page 137: ...Table 65 Jitter Values for Figure 76 Jitter Bandwidth 693 493 MHz Jitter RMS Broadband 1 kHz to 10 MHz 243 fs OC 48 12 kHz to 20 MHz 265 fs OC 192 20 kHz to 80 MHz 264 fs OC 192 4 MHz to 80 MHz 124 fs OC 192 50 kHz to 80 MHz 255 fs Broadband 800 Hz to 80 MHz 269 fs ...

Page 138: ...Hz 297 fs 265 fs OC 192 20 kHz to 80 MHz 309 fs 264 fs OC 192 4 MHz to 80 MHz 196 fs 124 fs OC 192 50 kHz to 80 MHz 301 fs 255 fs Broadband 800 Hz to 80 MHz 313 fs 269 fs 86 685 MHz in 173 371 MHz and 693 493 MHz out 1 80E 02 1 60E 02 1 40E 02 1 20E 02 1 00E 02 8 00E 01 6 00E 01 4 00E 01 2 00E 01 0 00E 00 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Phase Nois...

Page 139: ...Si53xx RM Rev 0 52 139 Figure 78 86 685 MHz In 173 371 MHz Out ...

Page 140: ...Si53xx RM 140 Rev 0 52 Figure 79 86 685 MHz In 693 493 MHz Out ...

Page 141: ...o 20 MHz 249 fs 251 fs OC 192 20 kHz to 80 MHz 274 fs 271 fs OC 192 4 MHz to 80 MHz 166 fs 164 fs OC 192 50 kHz to 80 MHz 267 fs 262 fs Broadband 800 Hz to 80 MHz 274 fs 363 fs 155 52 MHz and 156 25MHz in 622 08 MHz out 0 00E 00 6 00E 01 4 00E 01 2 00E 01 Bc Hz 1 00E 02 8 00E 01 6 00E 01 ase Noise dB 1 40E 02 1 20E 02 Pha 1 60E 02 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offs...

Page 142: ...Si53xx RM 142 Rev 0 52 Figure 81 10 MHz In 1 GHz Out ...

Page 143: ...e equipment Agilent model JS500 Jitter Band Jitter Brick Wall 10 Hz to 20 MHz 2 42 ps RMS Peak to peak 14 0 ps 27 MHz in 148 5 MHz out 160 140 120 100 80 60 40 20 0 10 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequency Hz Phase Noise dBc Hz ...

Page 144: ...INT FOS2_FLG FOS2_MSK in out Sticky Write 0 to clear FOS1_INT FOS1_FLG FOS1_MSK in out Sticky Write 0 to clear LOS2_INT LOS2_FLG LOS2_MSK in out Sticky Write 0 to clear LOS1_INT LOS1_FLG LOS1_MSK WIDEBAND MODE INT_POL FOS1_EN LOS1 EN INT_C1B E 1 0 CK1_BAD_PIN INT_PIN CK_BAD_POL LOS1_INT LOS Detector FOS Detector CKIN1 LOS2_EN C2B E CK2_BAD_PIN CK_BAD_POL LOS2_INT LOS Detector FOS Detector CKIN2 PD...

Page 145: ...Write 0 to clear 26 B 17 26 B 26 B06 in out Sticky Write 0 to clear 26 B 17 26 B 26 B06 in out Sticky Write 0 to clear 26 B 17 26 B 26 B06 in out Sticky Write 0 to clear 26 B 17 26 B 26 B06 in out Sticky Write 0 to clear 26 B 17 26 B 26 B06 in out Sticky Write 0 to clear 26 B 17 26 B 26 B06 in out Sticky Write 0 to clear 1B 17 1B 1B06 WIDEBAND MODE 17B32 LOS Detector FOS Detector 26 B 1 26B 1 26 B...

Page 146: ...tor 26 B 1 26 B 1 26 B 17 C3B E B B32 LOS Detector FOS Detector 26 B 1 26 B 1 26 B 17 C1B E 1 0 LOS Detector FOS Detector 26 B 1 26 B 1 26 B 17 C2B E 1 0 26 B 17 B 21 B5 6 1 B6 7 B5 B B3 1 B 21 B5 B B3 1 B B3 1 CKIN2 CKIN1 CKIN3 3 B 3 B 3 B 26B 1 26B 1 26B 1 6 1 B6 7 B5 LV DOZD V KLJK IRU DQ 6L ...

Page 147: ...lup Down Pin Si5316 Pull 1 RST U 11 RATE0 U D 14 DBL2_BY U D 15 RATE1 U D 21 CS U D 22 BWSEL0 U D 23 BWSEL1 U D 24 FRQSEL0 U D 25 FRQSEL1 U D 26 CK1DIV U D 27 CK2DIV U D 30 SFOUT1 U D 33 SFOUT0 U D Table 69 Si5322 Pullup Down Pin Si5322 Pull 1 RST U 2 FRQTBL U D 9 AUTOSEL U D 14 DBL2_BY U D 21 CS_CA U D 22 BWSEL0 U D 23 BWSEL1 U D 24 FRQSEL0 U D 25 FRQSEL1 U D 26 FRQSEL2 U D 27 FRQSEL3 U D 30 SFOU...

Page 148: ..._BY U D 15 RATE1 U D 19 DEC D 20 INC D 21 CS_CA U D 22 BWSEL0 U D 23 BWSEL1 U D 24 FRQSEL0 U D 25 FRQSEL1 U D 26 FRQSEL2 U D 27 FRQSEL3 U D 30 SFOUT1 U D 33 SFOUT0 U D Table 71 Si5319 Si5324 Pullup Down Pin Si5326 Pull 1 RST U 11 RATE0 U D 15 RATE1 U D 21 CS_CA U D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U D ...

Page 149: ...Si5325 Pull 1 RST U 21 CS_CA U D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U D Table 73 Si5326 Pullup Down Pin Si5326 Pull 1 RST U 11 RATE0 U D 15 RATE1 U D 19 DEC D 20 INC D 21 CS_CA U D 22 SCL D 24 A0 D 25 A1 D 26 A2_SS D 27 SDI D 36 CMODE U D ...

Page 150: ... A1 D 26 A2_SS D 27 SDI D 36 CMODE U D Table 75 Si5365 Pullup Down Pin Si5365 Pull 3 RST U 4 FRQTBL U D 13 CS0_C3A D 22 AUTOSEL U D 37 DBL2_BY U D 50 DSBL5 U D 57 CS1_C4A U D 60 BWSEL0 U D 61 BWSEL1 U D 66 DIV34_0 U D 67 DIV34_1 U D 68 FRQSEL0 U D 69 FRQSEL1 U D 70 FRQSEL2 U D 71 FRQSEL3 U D 80 SFOUT1 U D 85 DBL34 U 95 SFOUT0 U D ...

Page 151: ..._SW D 21 FS_ALIGN D 22 AUTOSEL U D 32 RATE0 U D 37 DBL2_BY U D 42 RATE1 U D 50 DBL_FS U D 51 CK_CONF D 54 DEC D 55 INC D 56 FOS_CTL U D 57 CS1_C4A U D 60 BWSEL0 U D 61 BWSEL1 U D 66 DIV34_0 U D 67 DIV34_1 U D 68 FRQSEL0 U D 69 FRQSEL1 U D 70 FRQSEL2 U D 71 FRQSEL3 U D 80 SFOUT1 U D 85 DSBL34 U 95 SFOUT0 U D ...

Page 152: ...CS0_C3A D 57 CS1_C4A U D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U D Table 78 Si5368 Pullup Down Pin Si5368 Pull 3 RST U 13 CS0_C3A D 21 FS_ALIGN D 32 RATE0 U D 42 RATE1 U D 54 DEC D 55 INC D 57 CS1_C4A U D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U D ...

Page 153: ...3A D 21 FS_ALIGN D 32 RATE0 U D 42 RATE1 U D 57 CS1_C4A U D 60 SCL D 68 A0 D 69 A1 D 70 A2_SSB D 71 SDI D 90 CMODE U D Table 80 Si5374 75 Pullup Down Pin Si5374 75 Pull D4 RSTL_A U D6 RSTL_B U F6 RSTL_C U F4 RSTL_D U D1 CS_CA_A U D A6 CS_CA_B U D F9 CS_CA_C U D J4 CS_CA_A U D G5 SCL D ...

Page 154: ...S Jitter RMS Broadband 1000 Hz to 10 MHz 296 fs 294 fs 2 426 fs 249 fs OC 48 12 kHz to 20 MHz 303 fs 304 fs 2 281 fs 236 fs OC 192 20 kHz to 80 MHz 321 fs 319 fs 3 079fs 352 fs OC 192 4 MHz to 80 MHz 169 fs 165 fs 2 621 fs 305 fs OC 192 50 kHz to 80 MHz 304 fs 303 fs 3 078 fs 340 fs Broadband 800 Hz to 80 MHz 329 fs 325 fs 3 076 fs 370 fs Dark blue normal locked Pink bypass Light blue digital hold...

Page 155: ...Si53xx RM Rev 0 52 155 Power Supply Noise Rejection Power Supply Noise to Output Transfer Function 105 100 95 90 85 80 75 70 65 60 1 10 100 1000 kHz dB 38 88 MHz in 155 52 MHz out Bandwidth 110 Hz ...

Page 156: ...loop Bandwidth 155 521 MHz in 622 084 MHz out 155 52 MHz Xtalk In digital hold OC 48 12 kHz to 20 MHz 262 fs 262 fs 269 fs 422 fs 255 fs OC 192 20 kHz to 80 MHz 287 fs 290 fs 296 fs 366 fs 280 fs Broadband 800 Hz to 80 MHz 285 fs 289 fs 298 fs 1 010 fs 277 fs Measurement conditions 1 Using Si5365 66 EVB 2 Clock input on CKIN1 a 0dBm sine wave from Rohde and Schwarz RF Generator model SML03 3 Cross...

Page 157: ...talk low bandwidth Yellow With crosstalk high bandwidth Red With crosstalk in digital hold 1 5 5 5 2 1 M H z in 6 2 2 0 8 4 M H z o u t 18 0 16 0 14 0 12 0 10 0 8 0 6 0 4 0 2 0 0 1 00 1 0 0 0 1 0 0 0 0 1 0 0 0 0 0 1 0 0 0 0 0 0 1 0 0 00 0 0 0 1 0 0 00 0 0 0 0 O ffs e t F re q u e n c y H z Phase Noise dBc Hz ...

Page 158: ...w Dark blue No crosstalk Light blue With crosstalk low bandwidth Yellow With crosstalk high bandwidth Red With crosstalk in digital hold 155 521 MHz in 622 084 MHz ou t 130 120 110 100 90 80 70 60 100 1000 10000 100000 Offset Frequency Hz Phase Noise dBc Hz ...

Page 159: ... fs RMS OC 192 20 kHz to 80 MHz 316 fs RMS 366 fs RMS Broadband 800 Hz to 80 MHz 340 fs RMS 1 010 fs RMS 155 521 M H z in 622 084 M H z out 180 160 140 120 100 80 60 40 20 0 100 1000 10000 100000 1000000 10000000 100000000 Offset Frequ ency Hz P h ase N oi se d B c Dark blue Bandwidth 6 72 kHz no Xtalk Light blue Bandwidth 6 72 kHz with Xtalk ...

Page 160: ...Si53xx RM 160 Rev 0 52 Clock Input Crosstalk Output of Rohde and Schwartz RF Rohde and Schwarz 155 521 M Hz 120 110 100 90 80 70 60 100 1000 Offse t Frequency Hz P h ase Noi se d Bc H ...

Page 161: ... to 10 MHz 282 fs 269 fs 257 fs 261 fs OC 48 12 kHz to 20 MHz 297 fs 289 fs 290 fs 291 fs OC 192 20 kHz to 80 MHz 315 fs 327 fs 358 fs 362 fs OC 192 4 MHz to 80 MHz 180 fs 222 fs 277 fs 281 fs OC 192 50 kHz to 80 MHz 299 fs 313 fs 348 fs 351 fs Broadband 800 Hz to 80 MHz 325 fs 332 fs 357 fs 360 fs 19 44 M Hz in 622 08 M Hz out 160 140 120 100 80 60 40 20 0 100 1000 10000 100000 1000000 10000000 1...

Page 162: ...t at 38 88 MHz Input frequency centered at 155 52 MHz then scanned Scan Ranges and Resolutions 50 ppm with 2 ppm steps 200 ppm with 10 ppm steps 2000 ppm with 50 ppm steps Output frequency always exactly four times the input frequency Centered at 622 08 MHz Jitter values are RMS integrated from 800 Hz to 80 MHz Figure 85 50 ppm 2 ppm Steps 38 88 MHz External XA XB Reference 0 200 400 600 800 1000 ...

Page 163: ...0 1200 155 49 155 5 155 51 155 52 155 53 155 54 155 55 Input Frequency MHz RMS jitter fs Input Frequency Variation 200 ppm 38 88 MHz External XA XB Reference 0 200 400 600 800 1000 1200 155 2 155 3 155 3 155 4 155 4 155 5 155 5 155 6 155 6 155 7 155 7 155 8 155 8 155 9 155 9 Input Frequency MHz RMS jitter fs Input Frequency Variation 2000 ppm ...

Page 164: ...ted Table 82 Jitter Values Fmod Fdev Jitter Start RF Gen Si5326 Si5324 0 0 500 Hz 1 18 ps 283 fs 281 fs 50 Hz 50 Hz 10 Hz 181 ps 169 ps 10 6 ps 100 Hz 100 Hz 50 Hz 177 ps 136 ps 2 04 ps 500 Hz 500 Hz 100 Hz 175 ps 18 6 ps 295 fs 1 kHz 1 kHz 500 Hz 184 ps 4 28 ps 292 fs 5 kHz 5 kHz 500 Hz 138 ps 297 fs 302 fs 10 kHz 10 kHz 500 Hz 139 ps 302 fs 304 fs Notes 1 All phase noise plots are with 622 08 MH...

Page 165: ...0E 01 0 00E 00 1 00E 01 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Phase Noise dBc Hz Blue RF Generator Green Si5326 Red Si5324 622 08 MHz in 622 08 MHz out 1 80E 02 1 60E 02 1 40E 02 1 20E 02 1 00E 02 8 00E 01 6 00E 01 4 00E 01 2 00E 01 0 00E 00 1 00E 01 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Phase Noise dBc Hz Bl...

Page 166: ...0E 01 0 00E 00 1 00E 01 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Phase Noise dBc Hz Blue RF Generator Green Si5326 Red Si5324 1 80E 02 1 60E 02 1 40E 02 1 20E 02 1 00E 02 8 00E 01 6 00E 01 4 00E 01 2 00E 01 0 00E 00 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Phase Noise dBc Hz Offset Frequency Hz 622 08 MHz in 622 08 MHz out Blue RF Gen...

Page 167: ... 2 00E 01 0 00E 00 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Phase Noise dBc Hz Blue RF Generator Green Si5326 Red Si5324 622 08 MHz in 622 08 MHz out 1 80E 02 1 60E 02 1 40E 02 1 20E 02 1 00E 02 8 00E 01 6 00E 01 4 00E 01 2 00E 01 0 00E 00 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Phase Noise dBc Hz Blue RF Generato...

Page 168: ...Jitter 622 08 MHz in 622 08 MHz out 1 80E 02 1 60E 02 1 40E 02 1 20E 02 1 00E 02 8 00E 01 6 00E 01 4 00E 01 2 00E 01 0 00E 00 1 00E 02 1 00E 03 1 00E 04 1 00E 05 1 00E 06 1 00E 07 1 00E 08 Offset Frequency Hz Phase Noise dBc Hz Blue RF Generator Green Si5326 Red Si5324 ...

Page 169: ...ard User s Guide Figure 95 Vdd Plane Use a solid and undisturbed ground plane for the Si537x and all of the clock input and output return paths For applications that wish to logically connect the four RSTL_x signals do not tie them together underneath the BGA package Instead connect them outside of the BGA footprint Where possible place the CKOUT and CKIN signals on separate PCB layers with a grou...

Page 170: ...quency value within the VCO range If a drifting VCO happens to have a frequency value that is close to an operational DSPLLs VCO there could be crosstalk between the two VCOs To avoid this issue Si537x DSPLLsim initializes the four DSPLLs with default Free Run frequency plans so that the VCO values are apart from one another If the four RSTL_x pins are directly connected to one another the connect...

Page 171: ...layout is critical to achieving the highest levels of jitter performance The following images were taken from the Si537x EVB evaluation board layout For more details about this board please refer to the Si537x EVB Evaluation Board User s Guide Figure 97 Output Clock Routing As much as is possible do not route clock input and outputsignals underneaththe BGApackage The clock outputsignals should go ...

Page 172: ...53xx RM 172 Rev 0 52 Figure 98 OSC_P OSC_N Routing OSC_P OSC_N Avoidplacing the OCS_P andOSC_N signals onthe same layer as the clock outputs Add grounded guard traces surrounding the OSC_PandOSC_N signals ...

Page 173: ...cies that are close in value to one another but not exactly the same Si5374 Si5375 Crosstalk Test Bed All four DSPLLs share the same frequency plan 38 88 MHz input 38 88 MHz x 4080 227 698 81 MHz output rounded There are four slightly different input frequencies DSPLL A 38 88 MHz 0 ppm 38 88000000 MHz DSPLL B 38 88 MHz 1 ppm 38 88003888 MHz DSPLL C 38 88 MHz 10 ppm 38 88038880 MHz DSPLL D 38 88 MH...

Page 174: ...Si53xx RM 174 Rev 0 52 Figure 99 Si5374 Si5375 DSPLL A ...

Page 175: ...Si53xx RM Rev 0 52 175 Figure 100 Si5374 Si5375 DSPLL B ...

Page 176: ...Si53xx RM 176 Rev 0 52 Figure 101 Si5374 Si5375 DSPLL C ...

Page 177: ... For example there are two possible VCO values for a 622 08 MHz clock output frequency In this case DSPLLs A and C would have one VCO value while DSPLLs B and D would have a different VCO value In this way DSPLLs that are diagonally opposite will have the same VCO value but immediately adjacent DSPLLs will have different VCO values In general the lower the output frequency the greater the number o...

Page 178: ...Ls programmed with similar services which may have operating frequencies that are close but not exactly the same the following procedure is suggested Run Si537xDSPLLsim three times once each for OTN OTU Ethernet and SONET This will result in three register maps that are each comprised of four sub maps A B C and D as shown below Figure 103 To accommodate a combination of the three different service...

Page 179: ...Si53xx RM Rev 0 52 179 Figure 104 Ethernet Suggested P3A P1B P3C P2D Not recommended P3A P1A P3C P4D Ethernet SONET OTN OTU ...

Page 180: ... were both 10 24 MHz The four curves all use the same data but are graphed at different scales to illustrate typical gain vs frequency and peaking The last curve shows the jitter peaking in detail that is well below 0 1 dB Figure 105 Wide View of Jitter Transfer 90 000 80 000 70 000 60 000 50 000 40 000 30 000 20 000 10 000 0 000 10 000 0 1 1 10 100 1000 10000 gain dB Offset Frequency Hz Jitter Tr...

Page 181: ...er Figure 107 Zoomed Again View of Jitter Transfer Showing Peaking 10 000 8 000 6 000 4 000 2 000 0 000 2 000 0 1 1 10 100 1000 gain dB Offset Frequency Hz Jitter Transfer 2 000 1 500 1 000 0 500 0 000 0 500 0 1 1 10 100 gain dB Offset Frequency Hz Jitter Transfer ...

Page 182: ...Si53xx RM 182 Rev 0 52 Figure 108 Maximum Zoomed View of Jitter Peaking 0 200 0 150 0 100 0 050 0 000 0 050 0 100 1 10 gain dB Offset Frequency Hz Jitter Transfer ...

Page 183: ...igure 23 Jitter Tolerance Mask Template Simplified Section 4 Device Specifications Updated Figure 41 CMOS Termination 1 8 2 5 3 3 V Revision 0 42 to Revision 0 5 Added Si5327 Si5369 Si5374 and Si5375 Removed Si5319 and Si5323 from the spec tables Updated the typical phase noise plots Added new appendixes G H I and J Updated spec table values Added examples and diagrams throughout Revision 0 5 to R...

Page 184: ...erein Additionally Silicon Laboratories assumes no responsibility for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising o...

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