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S i 5 3 x x - R M
50
Rev. 0.52
The Si5316 can accept a CKIN1 input at a different frequency than the CKIN2 input. The frequency of one input
clock can be 1x, 4x, or 32x the frequency of the other input clock. The output frequency is always equal to the lower
of the two clock inputs and is set via the FRQSEL [1:0] pins. The frequency applied at each clock input is divided
down by a pre-divider as shown in the Figure 1 on page 16. These pre-dividers must be set such that the two
resulting clock frequencies, f3_1 and f3_2 must be equal and are set by the FRQSEL [1:0] pins. Input divider
settings are controlled by the CK1DIV and CK2DIV pins, as shown in Table 14.
Figure 24. Si5316 Divisor Ratios
Table 14. Input Divider Settings
CKnDIV
N3n Input Divider
L
1
M
4
H
32
Table 15. Si5316 Bandwidth Values
FRQSEL[1:0] Nominal Frequency Values (MHz)
LL
LM
LH
ML
MM
MH
BW[1:0]
19.44 MHz
38.88 MHz
77.76 MHz
155.52 MHz 311.04 MHz 622.08 MHz
HM
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
100 Hz
HL
210 Hz
210 Hz
200 Hz
200 Hz
200 Hz
200 Hz
MH
410 Hz
410 Hz
400 Hz
400 Hz
400 Hz
400 Hz
MM
1.7 kHz
1.7 kHz
1.6 kHz
1.6 kHz
1.6 kHz
1.6 kHz
ML
7.0 kHz
7.0 kHz
6.8 kHz
6.7 kHz
6.7 kHz
6.7 kHz
1,
4,
32
1,
4,
32
CKIN1
CKIN2
DSPLL
F
out
f
3
= F
out
f
3
One-to-one
frequency ratio
Summary of Contents for Si5316 Series
Page 2: ...Si53xx RM 2 Rev 0 52 ...
Page 110: ...Si53xx RM 110 Rev 0 52 Figure 48 sfout_5 LVPECL Figure 49 sfout_6 CML ...
Page 111: ...Si53xx RM Rev 0 52 111 Figure 50 sfout_7 LVDS ...
Page 127: ...Si53xx RM Rev 0 52 127 Figure 66 155 52 MHz In 622 08 MHz Out Loop BW 7 Hz Si5324 ...
Page 128: ...Si53xx RM 128 Rev 0 52 Figure 67 19 44 MHz In 156 25 MHz Out Loop BW 80 Hz ...
Page 129: ...Si53xx RM Rev 0 52 129 Figure 68 19 44 MHz In 156 25 MHz Out Loop BW 5 Hz Si5324 ...
Page 131: ...Si53xx RM Rev 0 52 131 Figure 70 61 44 MHz In 491 52 MHz Out Loop BW 7 Hz Si5324 ...
Page 132: ...Si53xx RM 132 Rev 0 52 Figure 71 622 08 MHz In 672 16 MHz Out Loop BW 6 9 kHz ...
Page 133: ...Si53xx RM Rev 0 52 133 Figure 72 622 08 MHz In 672 16 MHz Out Loop BW 100 Hz ...
Page 134: ...Si53xx RM 134 Rev 0 52 Figure 73 156 25 MHz In 155 52 MHz Out ...
Page 139: ...Si53xx RM Rev 0 52 139 Figure 78 86 685 MHz In 173 371 MHz Out ...
Page 140: ...Si53xx RM 140 Rev 0 52 Figure 79 86 685 MHz In 693 493 MHz Out ...
Page 142: ...Si53xx RM 142 Rev 0 52 Figure 81 10 MHz In 1 GHz Out ...
Page 174: ...Si53xx RM 174 Rev 0 52 Figure 99 Si5374 Si5375 DSPLL A ...
Page 175: ...Si53xx RM Rev 0 52 175 Figure 100 Si5374 Si5375 DSPLL B ...
Page 176: ...Si53xx RM 176 Rev 0 52 Figure 101 Si5374 Si5375 DSPLL C ...