Silicon Laboratories Si4700 Page 42 Programming Manual Download | Manualshive

Page: 42 / 256

background image

AN332

42

Confidential Rev. 0.2

Property 0x2205. TX_LIMITER_RELEASE_TIME

Sets the time required for the device to respond to audio level transitions from above the limiter threshold to below
the limiter threshold. The CTS bit (and optional interrupt) is set when it is safe to send the next command. This
property may only be set or read when in powerup mode. The default is 5.01 ms, or 102.

Note:

TX_LIMITER_RELEASE_TIME is supported in FMTX component 2.0 or higher.

Default 0x0066 (102)

Step: 1

Range: 5–2000

Bit

D15 D14 D13 D12 D11 D10

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

Name

LIMITERTC[15:0]

Bit

Name

Function

15:0 LMITERTC[15:0]

Sets the limiter release time.

5 = 102.39 ms
6 = 85.33 ms
7 = 73.14 ms
8 = 63.99 ms
10 = 51.19 ms
13 = 39.38 ms
17 = 30.11 ms
25 = 20.47 ms
51 = 10.03 ms
57 = 8.97 ms
64 = 7.99 ms
73 = 7.01 ms
85 = 6.02 ms
102 = 5.01 ms (default)
127 = 4.02 ms
170 = 3.00 ms
255 = 2.00 ms
510 = 1.00 ms
1000 = 0.50 ms
2000 = 0.25 ms

«
...
40
41
42
43
44
...
»

Summary of Contents for Si4700

Page 1: ...s and responses The device has a slave control interface that allows the system controller to send commands to and receive responses from the device using one of three serial protocols or bus modes 2 wire mode I2C and SMBUS compatible 3 wire mode or SPI mode 6 Control Interface on page 168 describes the control interface in detail 7 Powerup on page 176 describes options for the sequencing of VDD a...

Page 2: ...7 WB Receiver with SAME 3 3 3x3 Si4710 FM Transmitter 3 3 3 3x3 Si4711 FM Transmitter with RDS 3 3 3 3 3x3 Si4712 FM Transmitter with RPS 3 3 3 3 3x3 Si4713 FM Transmitter with RDS RPS 3 3 3 3 3 3x3 Si4720 FM Transceiver 3 3 3 3 3 3x3 Si4721 FM Transceiver with RDS 3 3 3 3 3 3 3 3x3 Si4730 AM FM Receiver 3 3 3x3 Si4731 AM FM Receiver with RDS 3 3 3 3 3x3 Si4734 AM SW LW FM Receiver 3 3 3 3x3 Si473...

Page 3: ... 6 2 3 Wire Control Interface Mode 171 6 3 SPI Control Interface Mode 174 7 Powerup 176 7 1 Powerup from Device Memory 177 7 2 Powerup from a Component Patch 178 8 Powerdown 182 9 Digital Audio Interface 183 10 Timing 186 11 FM Transmitter 191 11 1 Audio Dynamic Range Control for FM Transmitter 191 11 2 Audio Pre emphasis for FM Transmitter 192 11 3 Audio Limiter for FM Transmitter 193 11 4 Maximi...

Page 4: ...LK External reference clock GPO General purpose output CTS Clear to send STC Seek Tune Complete NVM Non volatile internal device memory Device Refers to the FM Transmitter AM FM SW LW WB Receiver System Controller Refers to the system microcontroller CMD Command byte COMMANDn Command register 16 bit in 3 Wire mode n 1 to 4 ARGn Argument byte n 1 to 7 STATUS Status byte RESPn Response byte n 1 to 1...

Page 5: ...being sent from the device to the system controller The third column describes the action Properties are special command arguments used to modify the default device operation and are generally configured immediately after power up Examples of properties are TX _PREEMPHASIS and REFCLK_FREQ A complete list of properties is available in 5 Commands and Properties Table 3 shows an example of setting th...

Page 6: ...tatus bits 0x15 PATCH_ARGS Reserved command used for patch file downloads 0x16 PATCH_DATA Reserved command used for patch file downloads 0x30 TX_TUNE_FREQ Tunes to given transmit frequency 0x31 TX_TUNE_POWER Sets the output power level and tunes the antenna capacitor 0x32 TX_TUNE_MEASURE Si4712 13 20 21 Only Measure the received noise level at the specified frequency 0x33 TX_TUNE_STATUS Queries th...

Page 7: ...ut level to the LIN RIN pins to reach the maximum deviation level programmed into the audio deviation property TX Audio Deviation Default is 636 mVPK 0x327C 0x2105 TX_LINE_INPUT_MUTE Sets line input mute L and R inputs may be indepen dently muted Default is not muted 0x0000 0x2106 TX_PREEMPHASIS Configures pre emphasis time constant Default is 0 75 µS 0x0000 0x2107 TX_PILOT_FREQUENCY Configures th...

Page 8: ...fier 0x40A7 0x2C02 TX_RDS_PS_MIX2 Si4711 13 21 Only Configures mix of RDS PS Group with RDS Group Buffer 0x0003 0x2C03 TX_RDS_PS_MISC2 Si4711 13 21 Only Miscellaneous bits to transmit along with RDS_PS Groups 0x1008 0x2C04 TX_RDS_PS_REPEAT_COUNT2 Si4711 13 21 Only Number of times to repeat trans mission of a PS message before transmitting the next PS message 0x0003 0x2C05 TX_RDS_PS_MESSAGE_COUNT2 ...

Page 9: ...ext command 6 ERR Error 0 No error 1 Error 5 3 Reserved Values may vary 2 RDSINT RDS Interrupt 0 RDS interrupt has not been triggered 1 RDS interrupt has been triggered 1 ASQINT Signal Quality Interrupt 0 Signal quality measurement has not been triggered 1 Signal quality measurement has been triggered 0 STCINT Seek Tune Complete Interrupt 0 Tune complete has not been triggered 1 Tune complete has ...

Page 10: ...T interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt The CTSIEN bit is duplicated in the GPO_IEN property The command is complete when the CTS bit and optional interrupt is set Note To change function e g FM TX to FM RX issue the POWER_DOWN command to stop the current function then issu...

Page 11: ... X X RDSINT ASQINT STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RESP7 LIBRARYID 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of part number 2 7 0 FWMAJOR 7 0 Firmware Major Revision 3 7 0 FWMINOR 7 0 Firmware Minor Revision 4 7 0 RESERVED 7 0 Reserved v...

Page 12: ...D 0 0 0 1 0 0 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number 2 7 0 FWMAJOR 7 0 Firmware Major Revision 3 7 0 FWMINOR 7 0 Firmware Minor Revision 4 7 0 PATCHH 7 0 Patch ...

Page 13: ...ode If the system controller writes a command other than POWER_UP when in powerdown mode the device does not respond The device will only respond when a POWER_UP command is written Note In FMTX component 1 0 and 2 0 a reset is required when the system controller writes a command other than POWER_UP when in powerdown mode Command arguments None Response bytes None Command Response Bit D7 D6 D5 D4 D...

Page 14: ... 0 0 0 0 0 0 0 ARG2 PROPH 7 0 ARG3 PROPL 7 0 ARG4 PROPDH 7 0 ARG5 PROPDL 7 0 ARG Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 PROPH 7 0 Property High Byte This byte in combination with PROPL is used to specify the property to modify See Section 5 1 2 FM RDS Transmitter Properties on page 29 3 7 0 PROPL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the pro...

Page 15: ...rite to 0 2 7 0 PROPH 7 0 Property Get High Byte This byte in combination with PROPL is used to specify the property to get 3 7 0 PROPL 7 0 Property Get Low Byte This byte in combination with PROPH is used to specify the property to get Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X X RDSINT ASQINT STCINT RESP1 X X X X X X X X RESP2 PROPDH 7 0 RESP3 PROPDL 7 0 RESP Bit Name Function 1 7 0 Reserved...

Page 16: ...led to monitor the STATUS byte and when using interrupts this command should be called after the interrupt is set to update the STATUS byte The command is complete when the CTS bit and optional interrupt is set This command may only be sent when in powerup mode Command arguments None Response bytes One Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 1 0 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STA...

Page 17: ...erup mode The command clears the STC bit if it is already set See Figure 17 CTS and STC Timing Model on page 187 and Table 41 Command Timing Parameters for the FM Transmitter on page 188 Command arguments Three Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 0 0 ARG1 0 0 0 0 0 0 0 0 ARG2 FREQH 7 0 ARG3 FREQL 7 0 ARG Bit Name Function 1 7 0 Reserved Always write to ...

Page 18: ...e sent when in powerup mode The command clears the STC bit if it is already set See Figure 17 CTS and STC Timing Model on page 187 and Table 41 Command Timing Parameters for the FM Transmitter on page 188 Command arguments Four Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 0 1 ARG1 0 0 0 0 0 0 0 0 ARG2 0 0 0 0 0 0 0 0 ARG3 RFdBµV 7 0 ARG4 ANTCAP 7 0 ARG Bit Name ...

Page 19: ...s command may only be sent when in powerup mode The command clears the STC bit if it is already set See Figure 17 CTS and STC Timing Model on page 187 and Table 41 Command Timing Parameters for the FM Transmitter on page 188 Command arguments Three Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 1 0 ARG1 0 0 0 0 0 0 0 0 ARG2 FREQH 7 0 ARG3 FREQL 7 0 ARG4 ANTCAP 7 0...

Page 20: ...upt is set when it is safe to send the next command This command may only be sent when in powerup mode Command arguments One Response bytes Seven Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 0 1 1 ARG1 0 0 0 0 0 0 0 INTACK ARG Bit Name Function 1 7 1 Reserved Always write to 0 1 0 INTACK Seek Tune Interrupt Clear If set this bit clears the seek tune complete interrupt status indicato...

Page 21: ...ned 4 7 0 Reserved Returns various data 5 7 0 READRFdBµV 7 0 Read Power Returns the transmit output voltage setting 6 7 0 READANTCAP 7 0 Read Antenna Tuning Capacitor This byte will contain the current antenna tuning capacitor value 7 7 0 RNL 7 0 Read Received Noise Level Si4712 13 Only This byte will contain the receive level as the response to a TX Tune Mea sure command The returned value will b...

Page 22: ...d as reported by the OVERMOD bit in which case the host could reduce the audio level to the part If any of the OVERMOD IALH or IALL bits are set the ASQINT bit will also be set The ASQINT bit can be routed to a hardware interrupt via the GPO_IEN property Clearing the IALH or IALL interrupts will result in the TX_ASQ_DURATION_LOW or TX_ASQ_DURATION_HIGH counters being rearmed respectively to start ...

Page 23: ...el 1 Output signal is above requested modulation level 1 1 IALH Input Audio Level Threshold Detect High 0 Input audio level high threshold not exceeded 1 Input audio level high threshold exceeded 1 0 IALL Input Audio Level Threshold Detect Low 0 Input audio level low threshold not exceeded 1 Input audio level low threshold exceeded 2 7 0 Reserved Returns various values 3 7 0 Reserved Returns vario...

Page 24: ...es Five Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 1 0 1 0 1 ARG1 FIFO 0 0 0 0 LDBUFF MTBUFF INTACK ARG2 RDSBH 7 0 ARG3 RDSBL 7 0 ARG4 RDSCH 7 0 ARG5 RDSCL 7 0 ARG6 RDSDH 7 0 ARG7 RDSDL 7 0 ARG Bit Name Function 1 7 FIFO Operate on FIFO If set the command operates on the FIFO buffer If cleared the command operates on the circular buffer 1 6 3 Reserved Always write to 0 1 2 LDBUFF Load RDS Group...

Page 25: ...P2 CBAVAIL 7 0 RESP3 CBUSED 7 0 RESP4 FIFOAVAIL 7 0 RESP5 FIFOUSED 7 0 RESP Bit Name Function 1 7 5 Reserved Values may vary 1 4 RDSPSXMIT Interrupt source RDS PS Group has been transmitted 1 3 CBUFXMIT Interrupt source RDS Group has been transmitted from the FIFO buffer 1 2 FIFOXMIT Interrupt source RDS Group has been transmitted from the circular buffer 1 1 CBUFWRAP Interrupt source RDS Group Ci...

Page 26: ...3 PSCHAR1 7 0 ARG4 PSCHAR2 7 0 ARG5 PSCHAR3 7 0 ARG Bit Name Function 1 7 5 Reserved Always write to 0 1 4 0 PSID 4 0 Selects which PS data to load 0 23 0 First 4 characters of PS0 1 Last 4 characters of PS0 2 First 4 characters of PS1 3 Last 4 characters of PS1 22 First 4 characters of PS11 23 Last 4 characters of PS11 2 7 0 PSCHAR0 7 0 RDS PSID CHAR0 First character of selected PSID 3 7 0 PSCHAR...

Page 27: ...lly supported in FMTX component 3 0 or higher Only bit GPO3OEN is supported in FMTX comp 2 0 2 The use of GPO2 as an interrupt pin and or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and or GPO3 respectively Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 A...

Page 28: ...mode The default is all GPO pins set for high impedance Note GPIO_SET is fully supported in FMTX comp 3 0 or higher Only bit GPO3LEVEL is supported in FMTX comp 2 0 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Output Level...

Page 29: ... 0 No interrupt generated when RDSINT is already set default 1 Interrupt generated even if RDSINT is already set 9 ASQREP ASQ Interrupt Repeat 0 No interrupt generated when ASQREP is already set default 1 Interrupt generated even if ASQREP is already set 8 STCREP STC Interrupt Repeat 0 No interrupt generated when STCREP is already set default 1 Interrupt generated even if STCREP is already set 7 C...

Page 30: ...9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 IFALL IMODE 3 0 IMONO ISIZE 1 0 Bit Name Function 15 8 Reserved Always write to 0 7 IFALL DCLK Falling Edge 0 Sample on DCLK rising edge default 1 Sample on DCLK falling edge 6 3 IMODE 3 0 Digital Mode 0000 I2S Mode default 0110 Left justified mode 1100 MSB at 1st DCLK rising edge after DFS Pulse 1000 MSB at 2nd DCLK rising edge after DFS Pulse 2 I...

Page 31: ...The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Note DIGITAL_INPUT_SAMPLE_RATE is supported in FMTX component 2 0 or higher Default 0x0000 Units 1 Hz Step 1 Hz Range 0 32000 48000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name DISR 15 0 Bit Name Function 15 0 DISR Digital Input Sample Rate...

Page 32: ...hese RCLK gaps Figure 1 REFCLK Prescaler The RCLK must be valid 10 ns before and 10 ns after sending the TX_TUNE_MEASURE TX_TUNE_FREQ or TX_TUNE_POWER commands In addition the RCLK must be valid at all times when the carrier is enabled for proper AFC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command T...

Page 33: ...moved or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 1 Default 0x0001 Step 1 Range 1 4095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF 15 0 Bit Name Function 15 0 REFCLKF 15 0 Frequency of Reference Clock in Hz The allowed REFCLK fre...

Page 34: ... or read when in powerup mode The default is 6825 or 68 25 kHz Default 0x1AA9 6825 Units 10 Hz Step 10 Hz Range 0 9000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 RDS LMR PILOT Bit Name Function 15 3 Reserved Always write 0 2 RDS RDS Enable Si4711 13 21 Only 0 Disables RDS default 1 Enables RDS to be transmitted 1 LMR Left Minus Right 0 Disables Left Mi...

Page 35: ...nd optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 200 or 2 kHz Default 0x00C8 200 Units 10 Hz Step 10 Hz Range 0 9000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name TXPDEV 15 0 Bit Name Function 15 0 TXPDEV 15 0 Transmit Pilot Frequency Deviation Pilot tone frequency deviation is programma...

Page 36: ...uld keep the maximum line level on RIN LIN below 636 mVPK The Line Level would be set to 636 mVPK to correspond to the TX audio deviation level set by the TX_AUDIO_DEVIATION property The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default input level and peak line level is 636 mVPK with an input imped...

Page 37: ...ommand This property may only be set or read when in powerup mode The default is 75 µs Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LIMUTE RIMUTE Bit Name Function 15 2 Reserved Always write to 0 1 LIMUTE Mutes L Line Input 0 No mute default 1 Mute 0 RIMUTE Mutes R Line Input 0 No mute default 1 Mute Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 ...

Page 38: ...tively enables the audio dynamic range control and limiter The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is limiter enabled and audio dynamic range control disabled Note LIMITEN bit is supported in FMTX component 2 0 or higher Reset this bit to 0 in FMTX component 1 0 Default 0x0002 Bit D15 ...

Page 39: ...bove which the device applies the compression defined by gain threshold threshold The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 0xFFD8 or 40 dBFS Default 0xFFD8 40 Units 1 dB Step 1 dB Range 40 to 0 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name THRESHOLD 15 0 Bit Name Fun...

Page 40: ...t is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 0 5 ms or 0 Default 0x0000 Range 0 9 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 ATTACK 3 0 Bit Name Function 15 4 Reserved Always write to 0 3 0 ATTACK 3 0 Transmit Audio Dynamic Range Control Attack Time 0 0 5 ms default 1 1 0 ms 2...

Page 41: ...pplied to the audio below the threshold set by the TX_ACOMP_THRESHOLD property The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 15 dB or 0xF Default 0x000F 15 Units 1 dB Step 1 dB Range 0 20 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 RELEASE 2 0 ...

Page 42: ...owerup mode The default is 5 01 ms or 102 Note TX_LIMITER_RELEASE_TIME is supported in FMTX component 2 0 or higher Default 0x0066 102 Step 1 Range 5 2000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name LIMITERTC 15 0 Bit Name Function 15 0 LMITERTC 15 0 Sets the limiter release time 5 102 39 ms 6 85 33 ms 7 73 14 ms 8 63 99 ms 10 51 19 ms 13 39 38 ms 17 30 11 ms 25 20 47 ms 51 10 0...

Page 43: ...IEN bits The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 OVERMODIEN IALHIEN IALLIEN Bit Name Function 15 3 Reserved Always write to 0 2 OVERMODIEN Overmodulation Detection Enable 0 OVERMOD detect disabl...

Page 44: ... to 65535 ms and the default is 0 ms Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only return valid data after a call to TX_TUNE_FREQ TX_TUNE_POWER or TX_TUNE_MEASURE The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Default 0x0000 Units 1 ms S...

Page 45: ...n 1 ms increments that the input signal must be above the TX_ASQ_LEVEL_HIGH threshold in order for a IALH condition to be generated The range is 0 to 65535 ms and the default is 0 ms Note that the TX_ASQ_DURATION_LOW and TX_ASQ_DURATION_HIGH counters start and the TX_ASQ_STATUS command will only return valid data after a call to TX_TUNE_FREQ TX_TUNE_POWER or TX_TUNE_MEASURE The CTS bit and optiona...

Page 46: ... 0 0 0 0 0 0 RDS PSXMIT RDS CBUFXMIT RDSFI FOXMIT RDS CBUFWRAP RDSFI FOMT Bit Name Function 4 RDSPSXMIT 0 Do not interrupt default 1 Interrupt when a RDS PS Group has been transmitted The interrupt occurs when a PS group begins transmission 3 RDSCBUFXMIT 0 Do not interrupt default 1 Interrupt when a RDS Group has been transmitted from the Circular Buffer The interrupt occurs when a group is fetche...

Page 47: ...t command This property may only be set or read when in powerup mode Note TX_RDS_PS_MIX is supported in FMTX component 2 0 or higher Default 0x0003 Range 0 6 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RDSPI 15 0 Bit Name Function 15 0 RDSPI 15 0 Transmit RDS Program Identifier RDS program identifier data Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0...

Page 48: ...DSD3 Dynamic PTY code 0 Static PTY default 1 Indicates that the PTY code is dynamically switched 14 RDSD2 Compressed code 0 Not compressed default 1 Compressed 13 RDSD1 Artificial Head code 0 Not artificial head default 1 Artificial head 12 RDSD0 Mono Stereo code 0 Mono 1 Stereo default 11 FORCEB Use the PTY and TP set here in all block B data 0 FIFO and BUFFER use PTY and TP as when written defau...

Page 49: ...interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Note TX_RDS_PS_MESSAGE_COUNT is supported in FMTX component 2 0 or higher Default 0x0001 Range 1 12 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RDSPSRC 7 0 Bit Name Function 15 8 Reserved Always write to 0 7 0 RDSPSRC 7 0 Transmit RDS PS Repeat Cou...

Page 50: ...nd optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Note TX_RDS_PS_AF is supported in FMTX component 2 0 or higher Default 0xE0E0 Range 0xE000 0xE0CC Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RDSAF 15 0 Bit Name Function 15 0 RDSAF 15 0 Transmit RDS Program Service Alternate Frequency 0xE101 1 AF 87 6...

Page 51: ...e blocks through the TX_RDS_FIFO command as the buffer size may vary between versions or part numbers The guaranteed minimum FIFO size however is 53 blocks The RDS FIFO and the RDS Circular Buffer should be emptied with the TX_RDS_FIFO command prior to changing the size of the FIFO The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or r...

Page 52: ...O Si4705 06 21 31 35 37 39 41 49 only 0x27 FM_AGC_STATUS Queries the current AGC settings 0x28 FM_AGC_OVERRIDE Override AGC setting by disabling and forcing it to a fixed value 0x80 GPIO_CTL2 Configures GPO1 2 and 3 as output or Hi Z 0x81 GPIO_SET2 Sets GPO1 2 and 3 output level low or high Notes 1 RDS feature command FM_RDS_STATUS and property RDS_INT_SOURCE RDS_INT_FIFO_COUNT and RDS_CONFIG is s...

Page 53: ..._RSQ_SNR_HI_ THRESHOLD Sets high threshold for SNR interrupt 0x007F 0x1202 FM_RSQ_SNR_LO_ THRESHOLD Sets low threshold for SNR interrupt 0x0000 0x1203 FM_RSQ_RSSI_HI_ THRESHOLD Sets high threshold for RSSI interrupt 0x007F 0x1204 FM_RSQ_RSSI_LO_ THRESHOLD Sets low threshold for RSSI interrupt 0x0000 0x1205 FM_RSQ_MULTIPATH_HI_ THRESHOLD Sets high threshold for multipath interrupt Si4706 40 41 49 o...

Page 54: ... set this to 0 To force mono set this to 127 Default value is 30 dBμV Si4740 41 Only 0x001E 0x1802 FM_BLEND_RSSI_ ATTACK_RATE Sets the stereo to mono attack rate for RSSI based blend Smaller values provide slower attack and larger values provide faster attack The default is 1000 approximately 33 ms for 63 change Si4740 41 Only 0x03E8 0x1803 FM_BLEND_RSSI_ RELEASE_RATE Sets the mono to stereo relea...

Page 55: ...hange Si4740 41 Only 0x03E8 0x180B FM_BLEND_MULTIPATH_ RELEASE_RATE Sets the mono to stereo release rate for multipath based blend Smaller values provide slower release and larger values provide faster release The default is 10 approximately 3 3s for 63 change Si4740 41 Only 0x000A 0x4000 RX_VOLUME Sets the output volume Not applicable for Si4749 0x003F 0x4001 RX_HARD_MUTE Mutes the audio output L...

Page 56: ... Values may vary 3 RSQINT Received Signal Quality Interrupt 0 Received Signal Quality measurement has not been triggered 1 Received Signal Quality measurement has been triggered 2 RDSINT Radio Data System RDS Interrupt Si4705 06 21 31 35 37 39 41 49 Only 0 Radio data system interrupt has not been triggered 1 Radio data system interrupt has been triggered 1 Reserved Values may vary 0 STCINT Seek Tu...

Page 57: ...The command configures GPO2 INT interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt The CTSIEN bit is duplicated in the GPO_IEN property The command is complete when the CTS bit and optional interrupt is set Note To change function e g FM RX to AM RX or FM RX to FM TX issue POWER_DOWN co...

Page 58: ... component 2 0 or higher with XOSCEN 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RESP7 LIBRARYID 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of part number HEX 2 7 0 FWMAJOR 7 0 Firmware...

Page 59: ... D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number HEX 2 7 0 FWMAJOR 7 0 Firmware Major Revision ASCII 3 7 0 FWMINOR 7 0 Firmware Minor Revision ASCII 4 7 0 PATCHH 7 0 Patch ID Hi...

Page 60: ...POWER_UP when in powerdown mode Command arguments None Response bytes None Command Response Command 0x12 SET_PROPERTY Sets a property shown in Table 9 FM RDS Receiver Property Summary on page 52 The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode See Figure 18 CTS and SET_PROPERTY Command Complete tCOMP Timing Model ...

Page 61: ...OPL 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to modify 4 7 0 PROPDH 7 0 Property Value High Byte This byte in combination with PROPDL is used to set the property value 5 7 0 PROPDL 7 0 Property Value Low Byte This byte in combination with PROPDH is used to set the property value Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 0 1 1 ARG1 0 0 0 0 0 0 0 0 AR...

Page 62: ...ext command This command may only be set when in powerup mode Command arguments None Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT RDSINT X STCINT RESP1 0 0 0 0 0 0 0 0 RESP2 PROPDH 7 0 RESP3 PROPDL 7 0 RESP Bit Name Function 1 7 0 Reserved Always returns 0 2 7 0 PROPDH 7 0 Property Value High Byte This byte in combination with PROPDL represents the req...

Page 63: ... For FMRX components less than 2 0 tuning range is 76 108 MHz Command arguments Four Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 0 0 0 ARG1 0 0 0 0 0 0 0 0 ARG2 FREQH 7 0 ARG3 FREQL 7 0 ARG4 ANTCAP 7 0 ARG Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 FREQH 7 0 Tune Frequency High Byte This byte in combination with FREQL selects the tune frequency in 1...

Page 64: ...lled This command may only be sent when in powerup mode The command clears the STCINT bit if it is already set See Figure 17 CTS and STC Timing Model on page 187 and Table 42 Command Timing Parameters for the FM Receiver on page 188 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 0 0 1 ARG1 0 0 0 0 SEEKUP WRAP 0 0 ARG Bit Name Function 1 7 4 Res...

Page 65: ... be sent when in powerup mode Command arguments One Response bytes Seven Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 0 1 0 ARG1 0 0 0 0 0 0 CANCEL INTACK ARG Bit Name Function 1 7 2 Reserved Always write to 0 1 1 CANCEL Cancel seek If set aborts a seek currently in progress 1 0 INTACK Seek Tune Interrupt Clear If set clears the seek tune complete interrupt status indicator Bit D7 D6...

Page 66: ...ad Frequency High Byte This byte in combination with READFREQL returns frequency being tuned 10 kHz 3 7 0 READFREQL 7 0 Read Frequency Low Byte This byte in combination with READFREQH returns frequency being tuned 10 kHz 4 7 0 RSSI 7 0 Received Signal Strength Indicator This byte contains the receive signal strength when tune is complete dBµV 5 7 0 SNR 7 0 SNR This byte contains the SNR metric whe...

Page 67: ... be used to check if the detected multipath is above the Multipath high threshold as reported by MULTHINT or below the Multipath low threshold as reported by MULTLINT If the PILOT indicator is set it can also check whether the blend has crossed a threshold as indicated by BLENDINT The command clears the RSQINT BLENDINT SNRHINT SNRLINT RSSIHINT RSSILINT MULTHINT and MULTLINT interrupt bits when INT...

Page 68: ...ltipath low threshold 1 Detected multipath value has fallen below the Multipath low threshold 1 3 SNRHINT SNR Detect High 0 Received SNR has not exceeded above SNR high threshold 1 Received SNR has exceeded above SNR high threshold 1 2 SNRLINT SNR Detect Low 0 Received SNR has not fallen below SNR low threshold 1 Received SNR has fallen below SNR low threshold 1 1 RSSIHINT RSSI Detect High 0 RSSI ...

Page 69: ...ns the current receive signal strength 0 127 dBµV 5 7 0 SNR 7 0 SNR Contains the current SNR metric 0 127 dB 6 7 0 MULT 7 0 Multipath Si4706 40 41 49 Only Contains the current multipath metric 50 no multipath 0 full multipath 7 7 0 FREQOFF 7 0 Frequency Offset Signed frequency offset kHz ...

Page 70: ...ytes Twelve Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 0 1 0 0 ARG1 0 0 0 0 0 STATUSONLY MTFIFO INTACK ARG Bit Name Function 1 2 STATUSONLY Status Only Si4706 49 Only Determines if data should be removed from the RDS FIFO 0 Data in BLOCKA BLOCKB BLOCKC BLOCKD and BLE contain the oldest data in the RDS FIFO 1 Data in BLOCKA will contain the last valid block A data received for the cur...

Page 71: ... Lost 1 Lost RDS synchronization 1 0 RDSRECV RDS Received 1 FIFO filled to minimum number of groups set by RDSFIFOCNT 2 2 GRPLOST Group Lost 1 One or more RDS groups discarded due to FIFO overrun 2 0 RDSSYNC RDS Sync 1 RDS currently synchronized 3 7 0 RDSFIFOUSED RDS FIFO Used Number of groups remaining in the RDS FIFO 0 if empty If non zero BLOCKA BLOCKD contain the oldest FIFO entry and RDSFIFOU...

Page 72: ...ock D group data from oldest FIFO entry 11 7 0 BLOCKD 7 0 12 7 6 BLEA 1 0 RDS Block A Corrected Errors 0 No errors 1 1 2 bit errors detected and corrected 2 3 5 bit errors detected and corrected 3 Uncorrectable 12 5 4 BLEB 1 0 RDS Block B Corrected Errors 0 No errors 1 1 2 bit errors detected and corrected 2 3 5 bit errors detected and corrected 3 Uncorrectable 12 3 2 BLEC 1 0 RDS Block C Correcte...

Page 73: ...1 0 READ_RFAGCDIS This bit indicates whether the RF AGC is disabled or not 0 RF AGC is enabled 1 RF AGC is disabled 2 4 0 READ_LNA_GAIN_INDEX These bits returns the value of the LNA GAIN index 0 Minimum attenuation max gain 1 25 Intermediate attenuation 26 Maximum attenuation min gain Note the max index is subject to change ...

Page 74: ...Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 1 0 1 0 0 0 ARG1 X X X X X X X RFAGCDIS ARG2 X X X LNA_GAIN_INDEX 4 0 ARG Bit Name Function 1 0 RFAGCDIS This bit selects whether the RF AGC is disabled or not 0 RF AGC is enabled 1 RF AGC is disabled 2 4 0 LNA_GAIN_INDEX These bits set the value of the LNA GAIN index 0 Minimum attenuation max gain 1 25 Intermediate attenuation 26 Maximum attenuation mi...

Page 75: ...lly supported in FMRX component 2 0 or higher Only bit GPO3OEN is supported in FMRX comp 1 0 2 The use of GPO2 as an interrupt pin and or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and or GPO3 respectively Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 A...

Page 76: ...mode The default is all GPO pins set for high impedance Note GPIO_SET is fully supported in FMRX comp 2 0 or higher Only bit GPO3LEVEL is supported in FMRX comp 1 0 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Output Level...

Page 77: ... write to 0 11 RSQREP RSQ Interrupt Repeat 0 No interrupt generated when RSQINT is already set default 1 Interrupt generated even if RSQINT is already set 10 RDSREP RDS Interrupt Repeat Si4705 06 21 31 35 37 39 41 49 Only 0 No interrupt generated when RDSINT is already set default 1 Interrupt generated even if RDSINT is already set 9 Reserved Always write to 0 8 STCREP STC Interrupt Repeat 0 No in...

Page 78: ...0 No interrupt generated when STCINT is set default 1 Interrupt generated when STCINT is set Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 0 0 OFALL OMODE 3 0 OMONO OSIZE 1 0 Bit Name Function 15 8 Reserved Always write to 0 7 OFALL Digital Output DCLK Edge 0 use DCLK rising edge 1 use DCLK falling edge 6 3 OMODE 3 0 Digital Output Mode 0000 I2S 0110 Left justified 1000 MSB at second ...

Page 79: ...controller must establish DCLK and DFS prior to enabling the digital audio output else the device will not respond and will require reset Note DIGITAL_OUTPUT_SAMPLE_RATE is supported in FM receive component 2 0 or higher Digital Audio Output feature is not supported on Si4741 FMRX component 2A 7 Default 0x0000 digital audio output disabled Units sps Range 32 48 ksps 0 to disable digital audio outp...

Page 80: ... RCLK gaps Figure 2 REFCLK Prescaler The RCLK must be valid 10 ns before sending and 20 ns after completing the FM_TUNE_FREQ and FM_SEEK_START commands In addition the RCLK must be valid at all times for proper AFC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read...

Page 81: ...igured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 1 Default 0x0001 Step 1 Range 1 4095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF 15 0 Bit Name Function 15 0 REFCLKF 15 0 Frequency of Reference Clock in Hz The allowed REFCLK frequency range is...

Page 82: ...terrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 1 Default 0x0001 Range 0 4 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 DEEMPH 1 0 Bit Name Function 15 2 Reserved Always write to 0 1 0 DEEMPH 1 0 FM De Emphasis 10 75 µs Used in USA default 01 50 µs Used in Europe Australi...

Page 83: ...nd the next command This property may only be set or read when in powerup mode The default is 49 dBµV Default 0x0031 Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 STTHRESH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 STTHRESH FM Blend Stereo Threshold RSSI threshold below which the audio output goes into a blend mode Abo...

Page 84: ...is connected to the FMI pin Setting the FMTXO bit to 1 means that the antenna used is an embedded short antenna and it is connected to the TXO LPI pin Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MONOTHRESH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 MONOTHRESH FM Blend Mono Threshold RSSI threshold below which the audio output goes ...

Page 85: ...s property may only be set or read when in powerup mode The default is 30 kHz Default 0x001E Units kHz Step 1 Range 0 255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 FMMAXTUNEERR 7 0 Bit Name Function 15 8 Reserved Always write to 0 7 0 FMMAXTUNEERR FM Maximum Tuning Frequency Error Maximum tuning error allowed before setting the AFC Rail Indicator ON Specified i...

Page 86: ...e Multipath High Si4706 40 41 49 Only Enable Multipath high as the source of interrupt which the threshold is set by FM_RSQ_MULTIPATH_HI_THRESHOLD 4 MULTLIEN Interrupt Source Enable Multipath Low Si4706 40 41 49 Only Enable Multipath low as the source of interrupt which the threshold is set by FM_RSQ_MULTIPATH_LO_THRESHOLD 3 SNRHIEN Interrupt Source Enable SNR High Enable SNR high as the source of...

Page 87: ...next command This property may only be set or read when in powerup mode The default is 0 dB Default 0x0000 Units dB Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SNRH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 SNRH FM RSQ SNR High Threshold Threshold which triggers the RSQ interrupt if the SNR is above this threshold Specified in...

Page 88: ...ommand This property may only be set or read when in powerup mode The default is 0 dBµV Default 0x0000 Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 RSSIH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 RSSIH FM RSQ RSSI High Threshold Threshold which triggers the RSQ interrupt if the RSSI is above this threshold Specified ...

Page 89: ...eshold The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in power up mode The default is 0 Default 0x0000 Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 MULTH 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 MULTH FM RSQ Multipath High Threshold Threshold which ...

Page 90: ...is property may only be set or read when in powerup mode The default is 64 Default 64 Step 1 Range 1 255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 PILOT BLEND 6 0 Bit Name Function 15 8 Reserved Always write to 0 7 PILOT Pilot Indicator This bit has to be set to 1 there has to be a pilot present in order for FM_RSQ_BLEND_THRESHOLD to trigger an interrupt Withou...

Page 91: ...ro The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 4 dB Default 0x0004 Units dB Step 1 Range 0 15 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 SMATTN 4 0 Bit Name Function 15 5 Reserved Always write to 0 4 0 SMATTN FM Soft Mute Maximum Attenuation Set...

Page 92: ...is safe to send the next command This property may only be set or read when in powerup mode The default is 107 9 MHz Default 0x2A26 Units 10 kHz Step 50 kHz Range 64 108 MHz Note For FMRX components less than 2 0 range is 76 108 MHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name FMSKFREQL 15 0 Bit Name Function 15 0 FMSKFREQL FM Seek Band Bottom Frequency Selects the bottom of the ...

Page 93: ... in powerup mode The default is 3 dB Default 0x0003 Units dB Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 SKSPACE 4 0 Bit Name Function 15 5 Reserved Always write to 0 4 0 SKSPACE FM Seek Frequency Spacing Selects the frequency spacing during Seek function Specified in units of 10 kHz There are only 3 valid values 5 50 kHz 10 100 kHz and 2...

Page 94: ...6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 SKRSSI FM Seek Tune Received Signal Strength Threshold RSSI threshold which determines if a valid channel has been found during seek tune Specified in units of dBµV in 1 dBµV steps 0 127 Default is 20 dBµV Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 RDSNEW BLOCKB RDSNEW BLOCKA 0 RDSSYNC FOUND RDSSYN CL...

Page 95: ...interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode Default is 0 Note RDS_INT_FIFO_COUNT is supported in FMRX comp 2 0 or higher Default 0x0000 Range 0 14 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 RDSFIFOCNT 7 0 Bit Name Function 7 0 RDSFIFOCNT RDS FIFO Count Minimum number of RDS groups stored in...

Page 96: ...rected 3 3 3 3 Group stored regardless of errors 0 0 0 0 No group stored containing corrected or uncorrected errors 3 2 3 3 Group stored with corrected errors on B regardless of errors on A C or D Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name BLETHA 1 0 BLETHB 1 0 BLETHC 1 0 BLETHD 1 0 0 0 0 0 0 0 0 RDSEN Bit Name Function 15 14 BLETHA 1 0 Block Error Threshold BLOCKA 0 No errors ...

Page 97: ... This property may only be set or read when in powerup mode The default is 49 dBμV Default 0x0031 Units dBμV Step 1 Range 0 127 Property 0x1801 FM_BLEND_RSSI_MONO_THRESHOLD Si4740 41 Only Sets RSSI threshold for mono blend Full mono below threshold blend above threshold To force stereo set this to 0 To force mono set this to 127 The CTS bit and optional interrupt is set when it is safe to send the...

Page 98: ...nal interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 100 approximately 330ms for 63 change Default 0x0064 Step 1 Range 0 disabled 1 32767 Property 0x1804 FM_BLEND_SNR_STEREO_THRESHOLD Si4740 41 Only Sets SNR threshold for stereo blend Full stereo above threshold blend below threshold To force stereo set this to 0 To...

Page 99: ... optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 1000 approximately 33ms for 63 change Default 0x03E8 Step 1 Range 0 disabled 1 32767 Property 0x1807 FM_BLEND_SNR_RELEASE_RATE Si4740 41 Only Sets the mono to stereo release rate for SNR based blend Smaller values provide slower release and larger values pro...

Page 100: ...ext command This property may only be set or read when in powerup mode The default is 10 Default 0x000A Step 1 Range 0 50 Property 0x180A FM_BLEND_MULTIPATH_ATTACK_RATE Si4740 41 Only Sets the stereo to mono attack rate for Multipath based blend Smaller values provide slower attack and larger values provide faster attack The CTS bit and optional interrupt is set when it is safe to send the next co...

Page 101: ...xt command This property may only be set or read when in powerup mode The default is 63 Default 0x003F Step 1 Range 0 63 Property 0x4001 RX_HARD_MUTE Not applicable for Si4749 Mutes the audio output L and R audio outputs may be muted independently The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The defaul...

Page 102: ...ep 4 Range 4 248 Property 0x4101 RF_AGC_RELEASE_RATE Si4740 41 Only Sets the RF AGC release rate Larger values provide slower release and smaller values provide faster release The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 140 approximately 93 ms dB Default 0x008C Step 4 Range 4 248 Bit Na...

Page 103: ...o Si4730 31 34 35 36 37 Table 12 AM SW LW Receiver Command Summary Cmd Name Description 0x01 POWER_UP Power up device and mode selection 0x10 GET_REV Returns revision information on the device 0x11 POWER_DOWN Power down device 0x12 SET_PROPERTY Sets the value of a property 0x13 GET_PROPERTY Retrieves a property s value 0x14 GET_INT_STATUS Read interrupt status bits 0x15 PATCH_ARGS Reserved command...

Page 104: ...gh threshold for RSSI interrupt 0x007F 0x3204 AM_RSQ_RSSI_LOW_ THRESHOLD Sets low threshold for RSSI interrupt 0x0000 0x3300 AM_SOFT_MUTE_RATE Sets the attack and decay rates when entering or leaving soft mute The default is 278 dB s 0x0040 0x3301 AM_SOFT_MUTE_ SLOPE Sets the AM soft mute slope Default value is a slope of 2 0x0002 0x3302 AM_SOFT_MUTE_MAX_ ATTENUATION Sets maximum attenuation durin...

Page 105: ...es may vary 3 RSQINT Received Signal Quality Interrupt 0 Received Signal Quality measurement has not been triggered 1 Received Signal Quality measurement has been triggered 2 1 Reserved Values may vary 0 STCINT Seek Tune Complete Interrupt 0 Tune complete has not been triggered 1 Tune complete has been triggered Table 13 AM SW LW Receiver Property Summary Continued Prop Name Description Default No...

Page 106: ... digital audio mode The command configures GPO2 INT interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 INT is driven high during normal operation and low for a minimum of 1 µs during the interrupt The CTSIEN bit is duplicated in the GPO_IEN property The command is complete when the CTS bit and optional interrupt is set Note To change function e g AM SW LW RX to FM RX issue POWER...

Page 107: ...ly with XOSCEN 0 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RESP7 LIBRARYID 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of part number HEX 2 7 0 FWMAJOR 7 0 Firmware Major Revision ASCII 3 7 0 FWMI...

Page 108: ...Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 PATCHH 7 0 RESP5 PATCHL 7 0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number HEX 2 7 0 FWMAJOR 7 0 Firmware Major Revision ASCII 3 7 0 FWMINOR 7 0 Firmware Minor Revision ASCII 4 7 0 PATCHH 7 0 Patch ID High...

Page 109: ...nd Response Command 0x12 SET_PROPERTY Sets a property shown in Table 13 AM SW LW Receiver Property Summary on page 104 The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode See Figure 18 CTS and SET_PROPERTY Command Complete tCOMP Timing Model on page 187 and Table 43 Command Timing Parameters for the AM Receiver on pa...

Page 110: ...OPH is used to specify the property to modify See Section 5 3 2 AM SW LW Receiver Properties on page 120 4 7 0 PROPDH 7 0 Property Value High Byte This byte in combination with PROPDL is used to set the property value See Section 5 3 2 AM SW LW Receiver Properties on page 120 5 7 0 PROPDL 7 0 Property Value Low Byte This byte in combination with PROPDH is used to set the property value See Section...

Page 111: ... next command This command may only be set when in powerup mode Command arguments None Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT RESP1 0 0 0 0 0 0 0 0 RESP2 PROPDH 7 0 RESP3 PROPDL 7 0 RESP Bit Name Function 1 7 0 Reserved Always returns 0 2 7 0 PROPDH 7 0 Property Value High Byte This byte in combination with PROPDL represents the reques...

Page 112: ... 7 0 Reserved Always write to 0 2 7 0 FREQH 7 0 Tune Frequency High Byte This byte in combination with FREQL selects the tune frequency in kHz In AM SW LW mode the valid range is from 149 to 23000 149 kHz 23 MHz In AM only mode the valid range is from 520 to 1710 520 1710 kHz 3 7 0 FREQL 7 0 Tune Frequency Low Byte This byte in combination with FREQH selects the tune frequency in kHz In AM SW LW m...

Page 113: ...is command may only be sent when in powerup mode The command clears the STCINT bit if it is already set See Figure 17 CTS and STC Timing Model on page 187 and Table 43 Command Timing Parameters for the AM Receiver on page 189 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT X X STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 0 0 0 0 1 AR...

Page 114: ...be sent when in powerup mode Command arguments One Response bytes Seven Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 0 0 0 1 0 ARG1 0 0 0 0 0 0 CANCEL INTACK ARG Bit Name Function 1 7 2 Reserved Always write to 0 1 1 CANCEL Cancel seek If set aborts a seek currently in progress 1 0 INTACK Seek Tune Interrupt Clear If set clears the seek tune complete interrupt status indicator Bit D7 D6 ...

Page 115: ...d Frequency Low Byte This byte in combination with READFREQH returns frequency being tuned kHz 4 7 0 RSSI 7 0 Received Signal Strength Indicator This byte contains the receive signal strength when tune is completed dBµV 5 7 0 SNR 7 0 SNR This byte contains the SNR metric when tune is completed dB 6 7 0 READANTCAPH 15 8 Read Antenna Tuning Capacitor High Byte This byte in combination with READANTCA...

Page 116: ...old as reported by SNRLINT The command clears the RSQINT SNRHINT SNRLINT RSSIHINT and RSSILINT interrupt bits when INTACK bit of ARG1 is set The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode Command arguments One Response bytes Five Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 0 0 0 1 1 ARG1 0 0 0 0 0 0 0...

Page 117: ...t exceeded above RSSI high threshold 1 RSSI has exceeded above RSSI high threshold 1 0 RSSILINT RSSI Detect Low 0 RSSI has not exceeded below RSSI low threshold 1 RSSI has exceeded below RSSI low threshold 2 3 SMUTE Soft Mute Indicator Indicates soft mute is engaged 2 1 AFCRL AFC Rail Indicator Set if the AFC rails 2 0 VALID Valid Channel Set if the channel is currently valid and would have been f...

Page 118: ...ce Notes 1 GPIO_CTL is supported in AM_SW_LW component 2 0 or higher 2 The use of GPO2 as an interrupt pin and or the use of GPO3 as DCLK digital clock input will override this GPIO_CTL function for GPO2 and or GPO3 respectively Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7...

Page 119: ...r read when in powerup mode The default is all GPO pins set for high impedance Note GPIO_SET is supported in AM_SW_LW component 2 0 or higher Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Output Level 0 Output low default 1...

Page 120: ...CIEN Bit Name Function 15 12 Reserved Always write to 0 11 RSQREP RSQ Interrupt Repeat 0 No interrupt generated when RSQINT is already set default 1 Interrupt generated even if RSQINT is already set 10 9 Reserved Always write to 0 8 STCREP STC Interrupt Repeat 0 No interrupt generated when STCINT is already set default 1 Interrupt generated even if STCINT is already set 7 CTSIEN CTS Interrupt Enab...

Page 121: ...dio output else the device will not respond and will require reset Note DIGITAL_OUTPUT_SAMPLE_RATE is supported in AM_SW_LW receive component 2 0 or higher Default 0x0000 digital audio output disabled Units sps Range 32 48 ksps 0 to disable digital audio output Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name 0 0 0 0 0 0 0 0 OFALL OMODE 3 0 0 OSIZE 1 0 Bit Name Function 15 8 Reserved Always write to...

Page 122: ...FREQ and AM_SEEK_START commands In addition the RCLK must be valid at all times for proper AFC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 32768 Hz Default 0x8000 32768 Units 1 Hz Step 1 Hz Range 31130 34406 Table 15 RCLK ...

Page 123: ...nd This property may only be set or read when in powerup mode The default is 1 Default 0x0001 Step 1 Range 1 4095 Property 0x3100 AM_DEEMPHASIS Sets the AM Receive de emphasis to 50 µs The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is disabled Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 ...

Page 124: ... bandwidth is progressively reduced in seven steps to a minimum of 1 0 kHz The relationship between RSSI and bandwidth is The transition threshold is set midway between the specified RSSI values with 4 dB hysteresis Note The 1 kHz option is supported on AM_SW_LW component 2 A 2 or higher Default 0x0003 RSSI BW 89 6 000 kHz 83 4 000 kHz 77 3 564 kHz 71 3 175 kHz 65 2 828 kHz 59 2 520 kHz 53 2 245 k...

Page 125: ...ILIEN Bit Name Function 15 4 Reserved Always write 0 3 SNRHIEN Interrupt Source Enable SNR High Enable SNR high as the source of interrupt which the threshold is set by AM_RSQ_SNR_HI_THRESHOLD 2 SNRLIEN Interrupt Source Enable SNR Low Enable SNR low as the as the source of interrupt which the threshold is set by AM_RSQ_SNR_LO_THRESHOLD 1 RSSIHIEN Interrupt Source Enable RSSI High Enable RSSI low a...

Page 126: ...mmand This property may only be set or read when in powerup mode The default is 127 dB Default 0x007F Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 SNRL 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 SNRL AM RSQ SNR Low Threshold Threshold which triggers the RSQ interrupt if the SNR goes below this threshold Specified in u...

Page 127: ...d This property may only be set or read when in powerup mode The default rate is 278 dB s Default 0x0040 Actual Rate SMRATE x 4 35 Units dB s Step 1 Range 1 255 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 RSSIL 6 0 Bit Name Function 15 7 Reserved Always write to 0 6 0 RSSIL AM RSQ RSSI Low Threshold Threshold which triggers the RSQ interrupt if the RSSI goes be...

Page 128: ...mum attenuation during soft mute dB Set to 0 to disable soft mute The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default attenuation is 16 dB Default 0x0010 Units dB Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 SMSLOPE 3 0 Bit Name Function ...

Page 129: ...afe to send the next command This property may only be set or read when in powerup mode The default SNR threshold is 10 dB Default 0x000A Units dB Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 SMTHR 5 0 Bit Name Function 15 6 Reserved Always write to 0 5 0 SMTHR AM Soft Mute SNR Threshold The SNR threshold for a tuned frequency below which sof...

Page 130: ... is 520 kHz 0x0208 Default 0x0208 Units kHz Step 1 kHz Valid Range 149 23000 kHz Recommended Range AM in US 520 1710 kHz AM in Asia 522 1710 kHz SW 2300 23000 kHz LW 153 279 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name AMSKFREQL 15 0 Bit Name Function 15 0 AMSKFREQL AM Seek Band Bottom Specify the lower boundary of the AM band when performing a seek The seek either stops at t...

Page 131: ...lt for AM_SEEK_BAND_TOP After POWER_UP command is complete set AM_SEEK_BAND_TOP to 0x06AE 1710 kHz using the SET_PROPERTY command Units kHz Step 1 kHz Valid Range 149 23000 kHz Recommended Range AM in US 520 1710 kHz AM in Asia 522 1710 kHz SW 2300 23000 kHz LW 153 279 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name AMSKFREQH 15 0 Bit Name Function 15 0 AMSKFREQH AM Seek Band To...

Page 132: ... may only be set or read when in powerup mode The default frequency spacing is 10 kHz Default 0x000A Units kHz Valid Values 1 1 kHz 5 5 kHz 9 9 kHz and 10 10 kHz Recommended Value AM in US 10 10 kHz AM in Asia 9 9 kHz SW 5 5 kHz LW 9 9 kHz Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 AMSKSPACE 3 0 Bit Name Function 15 4 Reserved Always write to 0 3 0 AMSKS...

Page 133: ... next command This property may only be set or read when in powerup mode The default threshold is 5 dB Default 0x0005 Units dB Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 AMSKSNR 5 0 Bit Name Function 15 6 Reserved Always write to 0 5 0 AMSKSNR AM Seek Tune SNR Threshold SNR Threshold which determines if a valid channel has been found during...

Page 134: ...is safe to send the next command This property may only be set or read when in powerup mode The default is 63 Default 0x003F Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 AMSKRSSI 5 0 Bit Name Function 15 6 Reserved Always write to 0 5 0 AMSKRSSI AM Seek Tune Received Signal Strength Threshold RSSI Threshold which determines if a valid channel...

Page 135: ... when it is safe to send the next command This property may only be set or read when in powerup mode The default is unmute 0x0000 Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMUTE RMUTE Bit Name Function 15 2 Reserved Always write to 0 1 LMUTE Mutes both L and R Audio Outputs 0 RMUTE Mutes both L and R Audio Outputs ...

Page 136: ...served command used for patch file downloads 0x16 PATCH_DATA Reserved command used for patch file downloads 0x50 WB_TUNE_FREQ Selects the WB tuning frequency 0x52 WB_TUNE_STATUS Queries the status of previous WB_TUNE_FREQ or WB_SEEK_START command 0x53 WB_RSQ_STATUS Queries the status of the Received Signal Quality RSQ of the cur rent channel 0x54 WB_SAME_STATUS Retrieves Specific Area Message Enco...

Page 137: ...B_RSQ_SNR_HI_THRESHOLD Sets high threshold for SNR interrupt 0x007F 0x5202 WB_RSQ_SNR_LO_THRESHOLD Sets low threshold for SNR interrupt 0x0000 0x5203 WB_RSQ_RSSI_HI_THRESHOLD Sets high threshold for RSSI interrupt 0x007F 0x5204 WB_RSQ_RSSI_LO_THRESHOLD Sets low threshold for RSSI interrupt 0x0000 0x5403 WB_VALID_SNR_THRESHOLD Sets SNR threshold to indicate a valid channel 0x0003 0x5404 WB_VALID_RS...

Page 138: ...d Signal Quality Interrupt 0 Received Signal Quality measurement has not been triggered 1 Received Signal Quality measurement has been triggered 2 SAMEINT SAME Interrupt Si4707 only 0 SAME interrupt has not been triggered 1 SAME interrupt has been triggered 1 ASQINT Audio Signal Quality Interrupt 0 Audio Signal Quality measurement has not been triggered 1 Audio Signal Quality measurement has been ...

Page 139: ...3 WB Receive and the patch may be applied See Section 7 2 Powerup from a Component Patch on page xx The POWER_UP command configures the state of ROUT pin 13 LOUT pin 14 for analog audio mode The command configures GPO2 INT interrupts GPO2OEN and CTS interrupts CTSIEN If both are enabled GPO2 IRQ is driven high during normal operation and low for a minimum of 1 μs during the interrupt The CTSIEN bi...

Page 140: ... RAM but do not boot After CTS has been set RAM may be patched 1 4 XOSCEN Crystal Oscillator Enable 0 Use external RCLK crystal oscillator disabled 1 Use crystal oscillator RCLK and GPO3 DCLK with external 32 768kHz crystal and OPMODE 00000101 See Si47xx Data Sheet Application Schematic for external BOM details 1 3 0 FUNC 3 0 Function 3 WB Receive 0 2 4 14 Reserved 15 Query Library ID 2 7 0 OPMODE...

Page 141: ...US CTS ERR X X RSQINT SAMEINT ASQINT STCINT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 PN 7 0 RESP2 FWMAJOR 7 0 RESP3 FWMINOR 7 0 RESP4 RESERVED 7 0 RESP5 RESERVED 7 0 RESP6 CHIPREV 7 0 RESP7 LIBRARYID 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of part number HEX 2 7 0 FWMAJOR 7 0 Firmware Major Revision ASCII 3 7 0 FWMINOR 7 0 Firmware Minor Revi...

Page 142: ...0 RESP6 CMPMAJOR 7 0 RESP7 CMPMINOR 7 0 RESP8 CHIPREV 7 0 RESP Bit Name Function 1 7 0 PN 7 0 Final 2 digits of Part Number 2 7 0 FWMAJOR 7 0 Firmware Major Revision 3 7 0 FWMINOR 7 0 Firmware Minor Revision 4 7 0 PATCHH 7 0 Patch ID High Byte 5 7 0 PATCHL 7 0 Patch ID Low Byte 6 7 0 CMPMAJOR 7 0 Component Major Revision 7 7 0 CMPMINOR 7 0 Component Minor Revision 8 7 0 CHIPREV 7 0 Chip Revision ...

Page 143: ...spond when a POWER_UP command is written Command arguments None Response bytes None Command Response Command 0x12 SET_PROPERTY Sets a property shown in Table 17 WB Receive Property Summary on page 137 The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode Command Arguments Five Response bytes None Command Bit D7 D6 D5 D...

Page 144: ... 7 0 Property Low Byte This byte in combination with PROPH is used to specify the property to modify 4 7 0 PROPVH 7 0 Property Value High Byte This byte in combination with PROPVL is used to set the property value 5 7 0 PROPVL 7 0 Property Value Low Byte This byte in combination with PROPVH is used to set the property value Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 0 0 1 0 0 1 1 ARG1 0 0 0 0 0 0 0 0 ARG2 ...

Page 145: ...next command This command may only be sent when in powerup mode Command arguments None Response bytes One Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 0 0 0 0 0 0 0 0 RESP2 PROPVH 7 0 RESP3 PROPVL 7 0 RESP Bit Name Function 1 7 0 Reserved Always returns 0 2 7 0 PROPVH 7 0 Property Value High Byte This byte in combination with PROPVL will repres...

Page 146: ...t only after the GET_INT_STATUS command is called This command may only be sent when in powerup mode The command clears the STC bit if it is already set Command arguments Three Response bytes None Command Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 0 0 0 0 ARG1 0 0 0 0 0 0 0 0 ARG2 FREQH 7 0 ARG3 FREQL 7 0 Arg Bit Name Function 1 7 0 Reserved Always write to 0 2 7 0 FREQH 7 0 Tune Frequency High Byte ...

Page 147: ...and This command may only be sent when in powerup mode Command arguments One Response bytes Five Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 0 0 1 0 ARG1 0 0 0 0 0 0 0 INTACK Arg Bit Name Function 1 7 1 Reserved Always write to 0 1 0 INTACK Seek Tune Interrupt Clear If set this bit clears the seek tune complete interrupt status indicator Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X ...

Page 148: ...hen it is safe to send the next command This command may only be sent when in powerup mode Command arguments One Response bytes Seven Command Data Bit Name Function 1 7 2 Reserved Always returns 0 1 1 AFCRL AFC Rail Indicator This bit will be set if the AFC rails 1 0 VALID Valid Channel Confirms if the tuned channel is currently valid 2 7 0 READFREQH 7 0 Read Frequency High Byte This byte in combi...

Page 149: ...R low threshold 1 Received SNR has exceeded below SNR low threshold 1 1 RSSIHINT RSSI Detect High 0 RSSI has not exceeded above RSSI high threshold 1 RSSI has exceeded above RSSI high threshold 1 0 RSSILINT RSSI Detect Low 0 RSSI has not exceeded below RSSI low threshold 1 RSSI has exceeded below RSSI low threshold 2 1 AFCRL AFC Rail Indicator This bit will be set if the AFC rails 2 0 VALID Valid ...

Page 150: ...e previously received mes sage to increase the certainty of the message content After receipt of an End of Message this buffer must be cleared by the user To prevent different headers from being combined into an incorrect message the user must clear the buffer before a new header is transmitted As there is no indication that a new header is about to be transmitted the user must rely on other event...

Page 151: ...Name Function 1 3 EOMDET End Of Message Detected 1 End of message is detected 1 2 SOMDET Start Of Message Detected 1 start of message is detected 1 1 PREDET Preamble Detected 1 Preamble is detected 1 0 HDRRDY Header Buffer Ready 1 Header buffer is ready 2 7 0 STATE 7 0 State Machine Status 0 End of message 1 Preamble detected 2 Receiving SAME header message 3 SAME header message complete 3 7 0 MSG...

Page 152: ...TA2 represented as a number between 0 low and 3 high 5 3 2 CONF1 1 0 Confidence Metric for DATA1 represented as a number between 0 low and 3 high 5 1 0 CONF0 1 0 Confidence Metric for DATA0 represented as a number between 0 low and 3 high 6 7 0 DATA0 7 0 Byte of message read at address READADDR 0 7 7 0 DATA1 7 0 Byte of message read at address READADDR 1 8 7 0 DATA2 7 0 Byte of message read at add...

Page 153: ...rved 1 Clears ASQINT ALERTOFF_INT ALERTON_INT Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 X X X X X X ALERTOFF_INT ALERTON_INT RESP2 X X X X X X X ALERT Data Bit Name Function 1 1 ALERTOFF_INT ALERTOFF_INT 0 1050 Hz alert tone has not been detected to be absent since the last WB_TUNE_FREQ or WB_RSQ_STATUS with INTACK 1 1 1050 Hz alert tone has been detected to...

Page 154: ...sent when in powerup mode Command arguments None Response bytes One Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 0 1 1 1 Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT STCINT RESP1 X X X X X X X READ_RFAGCDIS RESP Bit Name Function 1 0 READ_RFAGCDIS This bit indicates whether the RF AGC is disabled or not 0 RF AGC is enabled 1 RF AGC is disabled ...

Page 155: ...attenuation This command may only be sent when in powerup mode Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 0 1 0 1 1 0 0 0 ARG1 X X X X X X X RFAGCDIS ARG Bit Name Function 1 0 RFAGCDIS This bit selects whether the RF AGC is disabled or not 0 RF AGC is enabled 1 RF AGC is disabled Bit D7 D6 D5 D4 D3 D2 D1 D0 STATUS CTS ERR X X RSQINT SAMEINT ASQINT ST...

Page 156: ...en in powerup mode The default is all GPO pins set for high impedance Note The use of GPO2 as an interrupt pin will override this GPIO_CTL function for GPO2 Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 0 ARG1 0 0 0 0 GPO3OEN GPO2OEN GPO1OEN 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3OEN GPO3 Output Enable 0 Output Disab...

Page 157: ...is property may only be set or read when in powerup mode The default is all GPO pins set for high impedance Command arguments One Response bytes None Command Response Bit D7 D6 D5 D4 D3 D2 D1 D0 CMD 1 0 0 0 0 0 0 1 ARG1 0 0 0 0 GPO3LEVEL GPO2LEVEL GPO1LEVEL 0 ARG Bit Name Function 1 7 4 Reserved Always write 0 1 3 GPO3LEVEL GPO3 Output Level 0 Output low default 1 Output high 1 2 GPO2LEVEL GPO3 Ou...

Page 158: ...I EN Bit Name Function 15 12 Reserved Always write to 0 11 RSQREP RSQ Interrupt Repeat 0 No interrupt generated when RSQINT is already set default 1 Interrupt generated even if RSQINT is already set 10 SAMEREP SAME Interrupt Repeat Si4707 Only 0 No interrupt generated when SAMEINT is already set default 1 Interrupt generated even if SAMEINT is already set 9 ASQREP ASQ Interrupt Repeat 0 No interru...

Page 159: ...carrier is enabled for proper AGC operation The RCLK may be removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode The default is 32768 Hz Default 0x8000 32768 Units 1 Hz 2 SAMEIEN SAME Interrupt Enable Si4707 Only 0 No interrupt generated when SAMEINT is set default 1 Interrupt ge...

Page 160: ... removed or reconfigured at other times The CTS bit and optional interrupt is set when it is safe to send the next command This command may only be sent when in powerup mode The default is 1 Default 0x0001 Step 1 Range 1 4095 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name REFCLKF 15 0 Bit Name Function 15 0 REFCLKF 15 0 Frequency of Reference Clock in Hz The allowed REFCLK frequenc...

Page 161: ...related to Received Signal Quality metrics The CTS bit and optional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 0 Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WBMAXTUNEERR 15 0 Bit Name Function 15 0 WBMAXTUNEERR WB Maximum Tuning Frequency Error Maximum tuning error allowed bef...

Page 162: ..._THRESHOLD 2 SNRLIEN Interrupt Source Enable Audio SNR Low Enable SNR low as the as the source of interrupt which the threshold is set by WB_RSQ_SNR_LO_THRESHOLD 1 RSSIHIEN Interrupt Source Enable RSSI High Enable RSSI high as the source of interrupt which the threshold is set by WB_RSQ_RSSI_HI_THRESHOLD 0 RSSILIEN Interrupt Source Enable RSSI Low Enable RSSI low as the source of interrupt which t...

Page 163: ...terrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 127dB Default 0x007F Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name SNRL 15 0 Bit Name Function 15 0 SNRL WB RSQ Audio SNR Low Threshold Threshold which will trigger the RSQ interrupt if the Audio SNR is below this threshold...

Page 164: ...ional interrupt is set when it is safe to send the next command This property may only be set or read when in powerup mode The default is 3dB Default 0x0003 Units dBµV Step 1 Range 0 127 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name RSSIL 15 0 Bit Name Function 15 0 RSSIL WB RSQ RSSI Low Threshold Threshold which will trigger the RSQ interrupt if the RSSI is below this threshold S...

Page 165: ... the next command This property may only be set or read when in powerup mode The default is 0 Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name WB_VALID_RSSI_THRESHOLD 15 0 Bit Name Function 15 0 WB_VALID_RSSI_ THRESHOLD WB Valid RSSI Threshold RSSI value at or above which WB_RSQ_STATUS and WB_TUNE_STATUS will consider the channel VALID Specified in units of dB in 1 dB ...

Page 166: ...his property may only be set or read when in powerup mode The default is 63 Default 0x003F Step 1 Range 0 63 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name X X X X X X X X X X X X X X ALERTOFF_IEN ALERTON_IEN Bit Name Function 1 ALERTOFF_IEN Interrupt Source Enable Alert OFF Enable 1050kHz alert tone disappeared as the source of interrupt 0 ALERTON_IEN Interrupt Source Enable Alert...

Page 167: ... when it is safe to send the next command This property may only be set or read when in powerup mode The default is unmute 0x0000 Default 0x0000 Bit D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 Name 0 0 0 0 0 0 0 0 0 0 0 0 0 0 LMUTE RMUTE Bit Name Function 15 2 Reserved Always write to 0 1 LMUTE Mutes both L and R Audio Outputs 0 RMUTE Mutes both L and R Audio Outputs ...

Page 168: ...s out of powerdown mode when the POWER_UP command is written to the command register Once in powerup mode the device accepts additional commands such as tuning and the setting of properties such as power level The device will not accept commands while in powerdown mode with the exception of the powerup command If the system controller writes a command other than POWER_UP when in powerdown mode the...

Page 169: ... control byte it will drive an eight bit data byte on SDIO changing the state of SDIO on the falling edges of SCLK The system controller acknowledges each data byte by driving SDIO low for one cycle on the next falling edge of SCLK If a data byte is not acknowledged by the system controller the transaction will end The system controller may read up to 16 data bytes in a single 2 wire transaction T...

Page 170: ...mand The system controller sets SDIO 1 indicated by NACK 1 to signal to the device the 2 wire transfer will end The system controller should set the STOP condition This process is repeated until the STATUS byte indicates that CTS bit is set 0x80 in this example When the STATUS byte returns CTS bit set 0x80 in this example the system controller may read the response bytes from the device The contro...

Page 171: ...f SCLK For read operations the control word is followed by a delay of one half SCLK cycle for bus turn around Next the device drives the 16 bit read data word serially on SDIO changing the state of SDIO on each rising edge of SCLK For read operations the control word is followed by a delay of one half SCLK cycle for bus turn around Next the device drives the 16 bit read data word serially on SDIO ...

Page 172: ...ponse byte stream are not guaranteed to be 0x00 and should be ignored For example GET_PROPERTY has 4 bytes of response data in registers RESPONSE1 RESPONSE2 The contents of registers RESPONSE3 RESPONSE8 are meaningless and not guaranteed to be 0x0000 Likewise for commands which have an odd number of response bytes or a single status byte the least significant byte bits 7 0 of the final register is...

Page 173: ...w one final time To read the status and response from the device the system controller sets SEN 0 Next the controller drives the 9 bit control word 101101000b on SDIO consisting of the device address A7 A5 101b the read bit 1b the device address A4 0 and the register address for the STATUS RESPONSE1 register A3 A0 1000b The control word is followed by a 16 bit data word consisting of STATUS follow...

Page 174: ...The device captures the data on rising edges of SCLK The control byte must have one of five values 0x48 write a command controller drives 8 additional bytes on SDIO 0x80 read a response device drives one additional byte on SDIO 0xC0 read a response device drives 16 additional bytes on SDIO 0xA0 read a response device drives one additional byte on GPO1 0xE0 read a response device drives 16 addition...

Page 175: ...STATUS byte In this example the STATUS byte is 0x00 indicating that the CTS bit bit 8 has not been set and that the response bytes are not ready for reading The device is not ready to accept another command The system controller sets SEN 1 to end the transfer This process should be repeated until the STATUS byte indicates that CTS bit is set 0x80 in this example When the STATUS byte indicates that...

Page 176: ...erup from Device Memory or from a firmware patch sent from the system controller see Section 7 2 Powerup from a Component Patch After CTS 1 the device is ready to commence normal operation and accept additional commands The POWER_UP command configures the state of DIN pin 13 DFS pin 14 and RIN pin 15 and LIN pin 16 for analog or digital audio modes and GPO2 INT for interrupt operation Prior to thi...

Page 177: ...igh or until a CTS interrupt is received if CTS interrupt is enabled 1 Send the POWER_UP command by writing the CMD field with value 0x01 2 Send ARG1 0x01 no patch CTS and GPO2 interrupts disabled AM SW LW receive selected Optionally various interrupts such as the CTS interrupt can be enabled by varying this argument see Section 5 Commands and Properties 3 Send ARG2 0x05 analog output selected 4 P...

Page 178: ... decrypt the patch Prior to downloading a partial patch the user must confirm that the device contains the correct firmware and library to support the patch 7 2 1 1 Examples An FM transmitter component patch for Si471x firmware 2 0 with library R4 does not support Si471x firmware 1 0 with library R0 For a programmatic indication the POWER_UP command can be used to confirm the device library and fi...

Page 179: ...f a leading command 0x15 or 0x16 and 7 arguments The controlling system must send each line of 8 bytes wait for a CTS then send the next set of 8 etc until the entire patch has been sent An example showing the first few lines and final line of a patch file is shown below Table 32 Si4730 31 Firmware Library and Component Compatibility Part Firmware Library FMRX Component AM_SW_LW RX Component Si473...

Page 180: ...e significantly less memory In 2 wire mode a full memory patch download requires approximately 500 ms at a 400 kHz clock rate The following is an example of the commands required to boot the device from powerdown mode using the patch file in the previous example The device has completed the boot process when the CTS bit is set high after the last byte in the file is transferred and is ready to acc...

Page 181: ...CII 0x41 revA Library ID HEX 0x04 library 4 CMD ARG1 ARG2 STATUS 0x01 0xE2 0x50 0x80 POWER_UP Set to FM Transmit set patch enable enable interrupts Set to Analog Line Input Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x15 0x00 0x0B 0x1D 0xBB 0x14 0xC4 0xA1 0x80 Reserved for Patch Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x16 0x...

Page 182: ...s enabled for proper AGC operation The RCLK may be removed or reconfigured at other times The RCLK is required for proper AGC operation when the carrier is enabled The RCLK may be removed or reconfigured when the carrier is disabled 3 Write POWER_DOWN to the command register Note that all register contents will be lost 4 Set RST 0 Note that RST must be held high for 10 ns after the completion of t...

Page 183: ...ransferring the digital audio data in DSP mode the MSB of the left channel can be transferred on the first rising edge of DCLK following the DFS pulse or on the second rising edge In all audio formats depending on the word size DCLK frequency and sample rates there may be unused DCLK cycles after the LSB of each word before the next DFS transition and MSB of the next word The number of audio bits ...

Page 184: ... to set the DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE property to 0 After changing or re enabling DCLK DFS user then can set the sample rate property again 5 The property DIGITAL_INPUT_FORMAT and DIGITAL_OUTPUT_FORMAT does not have a condition thus it can be set anywhere after power up Notes 1 Failure to provide DCLK and DFS prior to setting the sample rate property may cause the chi...

Page 185: ...PROPD STATUS 0x12 0x00 0x01 0x03 or 0x04 0x00 0x00 0x80 SET_PROPERTY DIGITAL_INPUT_SAMPLE_RATE or DIGITAL_OUTPUT_SAMPLE_RATE Sample rate 0 disable digital audio Reply Status Clear to send high Action User now is allowed to change or disabling DCLK DFS Action DCLK DFS has been changed or re enabled CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x03 or 0x04 0xBB 0x80 0x80 ...

Page 186: ...The CTS timing model is shown in Figure 16 and the timing parameters for each command are shown in Table 41 Figure 16 CTS Timing Model In addition to CTS bit there are a few commands e g TX_TUNE_FREQ or FM_TUNE_FREQ that use the STC bit to indicate that the command has completed execution It is highly recommended that user waits for the STC bit before sending the next command When interrupt is not...

Page 187: ...n rather the timing is guaranteed and it is called tCOMP The CTS and SET_PROPERTY command completion timing model tCOMP is shown in Figure 18 and the timing parameters for each command are shown in Table 41 Figure 18 CTS and SET_PROPERTY Command Complete tCOMP Timing Model Control Bus COMMAND GPO2 INT tSTC tCTS tINT tINT Control Bus COMMAND GPO2 INT tCOMP tCTS tINT ...

Page 188: ..._PS TX_TUNE_STATUS TX_TUNE_FREQ 100 ms TX_TUNE_MEASURE 100 ms TX_TUNE_POWER 20 ms SET_PROPERTY 10 ms GPIO_CTL GPIO_SET Table 42 Command Timing Parameters for the FM Receiver Command tCTS tSTC tCOMP tINT POWER_UP 110 ms 1 µs POWER_DOWN 300 µs GET_REV GET_PROPERTY GET_INT_STATUS FM_RSQ_STATUS FM_RDS_STATUS FM_TUNE_STATUS FM_TUNE_FREQ 60 ms FM_SEEK_START 60 ms SET_PROPERTY 10 ms FM_AGC_STATUS FM_AGC_...

Page 189: ...PROPERTY GET_INT_STATUS AM_RSQ_STATUS AM_TUNE_STATUS AM_TUNE_FREQ 80 ms AM_SEEK_START 80 ms SET_PROPERTY 10 ms GPIO_CTL GPIO_SET Note tSTC is seek time per channel Total seek time depends on bandwidth channel spacing and number of channels to next valid channel Worst case seek time complete for AM_SEEK_START is for USA AM Table 42 Command Timing Parameters for the FM Receiver FM_SEEK_BAND_TOP FM_S...

Page 190: ...for the WB Receiver Command tCTS tSTC tCOMP tINT POWER_UP 110 ms 1 µs POWER_DOWN 300 µs GET_REV GET_PROPERTY GET_INT_STATUS WB_RSQ_STATUS WB_SAME_STATUS WB_ASQ_STATUS WB_TUNE_STATUS WB_TUNE_FREQ 250 ms SET_PROPERTY 10 ms WB_AGC_STATUS WB_AGC_OVERRIDE GPIO_CTL GPIO_SET ...

Page 191: ...ld are compressed by a 2 to 1 dB ratio meaning that every 2 dB increase in audio input level above the threshold results in an audio output increase of 1 dB In this example the input dynamic range of 90 dB is reduced to an output dynamic range of 70 dB The FM Transmitter includes digital audio dynamic range control with programmable gain threshold attack rate and release rate The total dynamic ran...

Page 192: ...quency response Depending on the region a time constant of either 50 or 75 µs is used The frequency response of both of these filters is shown in Figure 21 For a 75 µs filter a 15 kHz tone is amplified by 17 dB For a 50 µs filter a 15 kHz tone is amplified by 13 5 dB The pre emphasis time constant is programmable to off 50 or 75 µs and is setting the TX_PREEMPHASIS property When using the pre emph...

Page 193: ... 4 Maximizing Audio Volume for FM Transmitter The audio input chain is shown in Figure 22 Figure 22 Audio Input Chain To maximize audio volume 1 Set the input line attenuation line level and audio deviation The input line attenuation should be set to the lowest setting that is above the maximum level provided by the audio source either 190 301 416 or 636 mVPK The line level should be set to the ma...

Page 194: ...input resistance of 60 kΩ An external series resistor on LIN and RIN inputs of 58 kΩ would create a resistive voltage divider that would keep the maximum line level on RIN LIN below 509 mVPK to give a 2 dB headroom With input signal at 509 mVPK 75 µs pre emphasis and the limiter enabled the Line Level can be set to 636 mVPK 2 Enable the audio dynamic range control In general the greater the sum of...

Page 195: ...silabs com as AN332SW 12 1 Programming Example for the FM RDS Transmitter The following flowchart is an overview of how to program the FM RDS transmitter RESET CHIP STATE POWER DOWN CHIP STATE POWER UP Power Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP command 0x01 Library ID Compatible w patch POWER_UP With Patch bit enabled command 0x01 Send Patch Data command ...

Page 196: ... Set RCLK settings property 0x0201 0x0202 Set ANALOG input settings 0x2104 Use Interrupt Digital Analog Use all default Settings Yes No No Set INT settings property 0x0001 Yes Set GPO command 0x80 0x81 Yes Use GPO No Enable digital audio by setting DFS sample rate property 0x0103 Clock must be available on DCLK DFS pin Set audio format property 0x0101 ...

Page 197: ...isable Stereo components property 0x2100 Stereo Mono Disable RDS components property 0x2100 Set RDS Deviation property 0x2103 Enable RDS components property 0x2100 Set RDS properties property 0x2C00 0x2C07 Send RDS PS Group Type0 command 0x36 Send any other RDS Group Type 1 15 Send RDS Group Type 1 15 command 0x35 Yes No Yes No Set Audio Deviation property 0x2101 ...

Page 198: ... No Compressor Enable Compressor Settings property 0x2200 04 Disable Compressor property 0x2200 Yes No Limiter Enable Limiter Settings property 0x2200 05 Disable Limiter property 0x2200 Yes No Set FM Transmit Frequency command 0x30 Set Transmit Power command 0x31 CHIP STATE TRANSMITTING Query TX_TUNE_STATUS command 0x33 ...

Page 199: ...e or Unmute Audio based on ASQ status property 0x2105 Want to find an empty channel Using RPS Si4712 13 2x only Send TX_TUNE_MEASURE command 0x32 Do host processing On returned RPS value To find empty channels CHIP STATE Received Idle Set FM Transmit Freq and or Power CHIP STATE TRANSMITTING Yes No Yes No LOOP from start_freq to end_freq until DONE ...

Page 200: ...ification is necessary Refer to Section 5 Commands and Properties on page 6 for a full description of each command and property Change Chip Function To FM Receive Si472x only Send POWER_DOWN command 0x11 Yes CHIP STATE POWER DOWN Send POWER_UP For FM Receive command 0x01 CHIP STATE POWER UP FM Receive Look at FM Receive Flowchart No TRANSMISSION DONE Yes Send POWER_DOWN command 0x11 CHIP STATE POW...

Page 201: ...nd high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x01 0x00 0x00 0x80 SET_PROPERTY DIGITAL_INPUT_FORMAT Mode I2S stereo 16bit sample on rising edge of DCLK Reply Status Clear to send high Action Go to Configuration bypass Powerup in analog mode section The rest of the programming is the same as analog Powerup in analog mode CMD ARG1 ARG2 STATUS 0x01 0xC2 0x50 0x80 PO...

Page 202: ...0xC1 0x80 SET_PROPERTY GPO_IEN Set STCIEN ERRIEN CTSIEN Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x01 0x7E 0xF4 0x80 SET_PROPERTY REFCLK_FREQ REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x02 0x01 0x90 0x80 SET_PROPERTY RCLK_PRESCALE Divide by 400 example RCLK...

Page 203: ...kHz 6825d 0x1AA9 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x02 0x02 0xA3 0x80 SET_PROPERTY TX_PILOT_DEVIATION 6 75 kHz 675d 0x2A3 Reply Status Clear to send high Tuning CMD ARG1 ARG2 ARG3 ARG4 STATUS 0x31 0x00 0x00 0x73 0x00 0x80 TX_TUNE_POWER Set transmit voltage to 115 dBµV 115d 0x73 Set antenna tuning capacitor to auto Reply Status...

Page 204: ...PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x22 0x01 0xFF 0xD8 0x80 SET_PROPERTY TX_ACOMP_THRESHOLD Threshold 40 dBFS 0xFFD8 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x22 0x04 0x00 0x0F 0x80 SET_PROPERTY TX_ACOMP_GAIN Gain 15 dB 0xF Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x...

Page 205: ...0x01 0x00 0xCE 0x80 SET_PROPERTY TX_ASQ_LOW_LEVEL 50 dB 0x00CE Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x23 0x02 0x27 0x10 0x80 SET_PROPERTY TX_ASQ_DURATION_LOW 10000 ms 0x2710 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x23 0x03 0x00 0xEC 0x80 SET_PROPERTY TX_ASQ_HIGH_LEVEL 20 dB 0...

Page 206: ...12 13 20 21 Only CMD ARG1 ARG2 ARG3 ARG4 STATUS 0x32 0x00 0x27 0x7E 0x00 0x80 TX_TUNE_MEASURE Set frequency to 101 1 MHz 10110d 0x277E Set antenna tuning capacitor to auto Reply Status Clear to send high CMD STATUS 0x14 0x81 GET_INT_STATUS Reply Status Clear to send high STCINT 1 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 0x33 0x01 0x80 0x00 0x27 0x7E 0x00 0x00 0xAB 0x32 TX_TUNE_STA...

Page 207: ...P ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x01 0x19 0xE1 0x80 SET_PROPERTY TX_AUDIO_DEVIATION 66 25 kHz 6625d 0x19E1 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x21 0x03 0x00 0xC8 0x80 SET_PROPERTY TX_RDS_DEVIATION Si4711 13 21 Only 2 kHz 200d 0xC8 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS ...

Page 208: ...21 Only Sets program service repeat count to 3 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x2C 0x05 0x00 0x03 0x80 SET PROPERTY TX_RDS_PS_MESSAGE_COUNT Si4711 13 21 Only Sets PS message count to 3 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x2C 0x06 0xE1 0x02 0x80 SET_PROPERTY TX_RDS_P...

Page 209: ...Complete text is SILABS SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS 0x36 0x03 0x31 0x58 0x20 0x20 0x80 TX_RDS_PS Si4711 13 21 Only PSID 3 Set text 1X Complete text is SILABS SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 STATUS 0x36 0x04 0x52 0x44 0x53 0x20 0x80 TX_RDS_PS Si4711 13 21 Only PSID 4 Set text RDS Complete text is SI...

Page 210: ...4 0x20 0x02 0x4C 0x41 0x42 0x4F 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 2 Set text LABO Complete text is SILICON LABORATORIES SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x35 0x04 0x20 0x03 0x52 0x41 0x54 0x4F 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 3 Set text RATO Complete text is S...

Page 211: ... 0x04 0x20 0x07 0x52 0x44 0x53 0x20 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 7 Set text RDS Complete text is SILICON LABORATORIES SI471X RDS DEMO Reply Status Clear to send high CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS 0x35 0x04 0x20 0x08 0x44 0x45 0x4D 0x4F 0x80 TX_RDS_BUFF Si4711 13 21 Only Set LDBUFF Set Group 2A Text Location 8 Set text DEMO Complete text i...

Page 212: ...to send high RDSINT 1 CMD ARG1 ARG2 ARG3 ARG4 ARG5 ARG6 ARG7 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 0x35 0x01 0x00 0x00 0x00 0x00 0x00 0x00 0x80 0x00 0x5E 0x1E 0x03 0x00 TX_RDS_BUFF Si4711 13 21 Only Clear RDSINT Reply Status Clear to send high No FIFO Overflow Circular buffer available 94 Circular buffer used 30 FIFO available 0 FIFO used 3 CMD STATUS 0x11 0x80 POWER_DOWN Reply Status Clear to send...

Page 213: ... DOWN CHIP STATE POWER UP Power Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP command 0x01 Library ID Compatible w patch POWER_UP With Patch bit enabled command 0x01 Send Patch Data command 0x15 0x16 Yes No Yes No Check Chip FW Comp rev GET_REV command 0x10 Chip FW Comp Rev are correct Contact Silabs For verification No Yes Contact Silabs For verification ...

Page 214: ...roperty 0x0104 Use Interrupt Use all default Settings Yes No No Set INT settings property 0x0001 Yes Set GPO command 0x80 0x81 Yes Use GPO No Yes No Which pin is used For the antenna Si4704 05 06 2x only Set FM_ANTENNA_INPUT property 0x1107 1 Set FM_ANTENNA_INPUT property 0x1107 0 TXO LPI pin for embedded short antenna FMI pin for headphone long antenna Clock must be available on DCLK DFS pin Set ...

Page 215: ... settings property 0x1105 06 Set Max Tune Error property 0x1108 Set Soft Mute Settings property 0x1300 02 03 Set FM Tune Frequency command 0x20 CHIP STATE RECEIVING FM Query FM_TUNE_STATUS command 0x22 Set Volume property 0x4000 Set Mute Unmute property 0x4001 Not applicable to Si4749 ...

Page 216: ...perty 0x1500 SetRDS_INT_FIFO_COUNT property 0x1501 Set RDS_CONFIG enable RDS property 0x1502 Yes Read RDS data with FM_RDS_STATUS command 0x24 Received RDS Interrupt or poll RDSINT from GET_INT_STATUS LOOP until RDS FIFO is empty Process RDS data on the host Disable RDS in RDS_CONFIG property 0x1502 No ...

Page 217: ...RSQ_STATUS SCAN FM Band For valid channels Store valid channels In the Host CHIP STATE RECEIVING FM Yes No Yes No LOOP until reaches End of FM band or Back to the original Channel Set SEEK settings property 0x1400 1404 Send FM_SEEK_START command 0x21 SEEK next Valid channel Set SEEK settings property 0x1400 1404 Send FM_SEEK_START command 0x21 Yes CHIP STATE RECEIVING FM No ...

Page 218: ... LW Receive Or WB Receive Flowchart No RECEIVE FM DONE Yes Send POWER_DOWN command 0x11 CHIP STATE POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in FM Receive Need to change DCLK DFS Rate digital only Disable digital audio by setting DFS sample rate to 0 property 0x0104 Change DCLK DFS rate...

Page 219: ...RDS Receiver Action Data Description Powerup in digital mode CMD ARG1 ARG2 STATUS 0x01 0xC0 0xB0 0x80 POWER_UP Set to FM Receive Enable interrupts Set to Digital Audio Output Reply Status Clear to send high Action Ensure that DCLK and DFS are already supplied CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x04 0xBB 0x80 0x80 SET_PROPERTY DIGITAL_OUTPUT_SAMPLE_RATE Sample ...

Page 220: ... Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x01 0x7E 0xF4 0x80 SET_PROPERTY REFCLK_FREQ REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x02 0x01 0x90 0x80 SET_PROPERTY REFCLK_PRESCALE Divide by 400 example RCLK 13 MHz REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 A...

Page 221: ...d 24 dBµV 0x0018 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x11 0x08 0x00 0x28 0x80 SET_PROPERTY FM_MAX_TUNE_ERROR Threshold 40 kHz 0x0028 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x12 0x00 0x00 0x8F 0x80 SET_PROPERTY FM_RSQ_INT_SOURCE Enable blend SNR high SNR low RSSI high and RSS...

Page 222: ...ROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x12 0x04 0x00 0x18 0x80 SET_PROPERTY FM_RSQ_RSSI_LO_THRESHOLD Threshold 24 dBµV 0x0018 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x12 0x07 0x00 0xB2 0x80 SET_PROPERTY FM_RSQ_BLEND_THRESHOLD Pilot 1 Threshold 50 0x0032 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PRO...

Page 223: ..._BAND_TOP Top Freq 107 9 MHz 0x2A26 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x14 0x02 0x00 0x14 0x80 SET_PROPERTY FM_SEEK_FREQ_SPACING Freq Spacing 200 kHz 0x0014 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x14 0x03 0x00 0x06 0x80 SET_PROPERTY FM_SEEK_TUNE_SNR_THRESHOLD Threshold 6 ...

Page 224: ...0x00 0x01 0xD9 0x2D 0x33 0x00 0x00 FM_RSQ_STATUS Clear RSQINT Reply Status Clear to send high No blend SNR high low RSSI high or low interrupts Soft mute is not engaged no AFC rail valid frequency Pilot presence 89 blend RSSI 45 dBµV SNR 51 dB Freq offset 0 kHz CMD ARG1 STATUS 0x21 0x0C 0x80 FM_SEEK_START Seek Up and Wrap Reply Status Clear to send high CMD STATUS 0x14 0x81 GET_INT_STATUS Reply St...

Page 225: ...T_PROPERTY RDS_CONFIG Set Block Error A B C D to 3 2 3 3 Enable RDS Reply Status Clear to send high CMD STATUS 0x14 0x84 GET_INT_STATUS Reply Status Clear to send high RDSINT 1 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x84 0x01 0x01 0x17 0x40 0xA7 0x20 0x00 0x53 0x49 0x4C 0x49 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to s...

Page 226: ...red Block D 0x5349 SI BLE 0 No Error Current PS SI Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x15 0x40 0xA7 0x20 0x01 0x43 0x4F 0x4E 0x20 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchroniz...

Page 227: ...3 4 Block C ignored Block D 0x4C41 LA BLE 0 No Error Current PS SILA Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x14 0x40 0xA7 0x20 0x02 0x4C 0x41 0x42 0x4F 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS recei...

Page 228: ...Block C ignored Block D 0x4253 BS BLE 0 No Error Current PS SILABS Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x13 0x40 0xA7 0x20 0x03 0x52 0x41 0x54 0x4F 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS receive...

Page 229: ...Block C ignored Block D 0x2020 BLE 0 No Error Current PS SILABS Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x12 0x40 0xA7 0x20 0x04 0x52 0x49 0x45 0x53 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received R...

Page 230: ...ck C ignored Block D 0x5244 RD BLE 0 No Error Current PS RDLABS Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x11 0x40 0xA7 0x20 0x05 0x20 0x53 0x49 0x34 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received R...

Page 231: ...5320 S BLE 0 No Error Current PS RDS BS Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0F 0x40 0xA7 0x20 0x06 0x37 0x31 0x58 0x20 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost ...

Page 232: ...urrent PS RDS DE Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0E 0x40 0xA7 0x20 0x07 0x52 0x44 0x53 0x20 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x0E...

Page 233: ...nt PS RDS DEMO Complete Scrolling PS SILABS RDS DEMO CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0D 0x40 0xA7 0x20 0x08 0x44 0x45 0x4D 0x4F 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x0D 1...

Page 234: ...US RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x24 0x01 0x80 0x01 0x01 0x0D 0x40 0xA7 0x20 0x09 0x0D 0x00 0x00 0x00 0x00 FM_RDS_STATUS Clear RDS interrupt Reply Status Clear to send CTS high Seek Tune Complete STCINT high Interrupt source RDS received RDS Synchronized No lost data RDS FIFO Used 0x0C 12 FIFO receives another group while querying Block A 0x40A7 PI Cod...

Page 235: ...OWN CHIP STATE POWER UP Power Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP command 0x01 Library ID Compatible w patch POWER_UP With Patch bit enabled command 0x01 Send Patch Data command 0x15 0x16 Yes No Yes No Check Chip FW Comp rev GET_REV command 0x10 Chip FW Comp Rev are correct Contact Silabs For verification No Yes Contact Silabs For verification ...

Page 236: ...CEIVING AM SW LW Digital output mode Si4731 35 37 only Set RCLK settings property 0x0201 0x0202 Set DIGITAL output settings property 0x0102 0x0104 Use Interrupt Use all default Settings Yes No No Set INT settings property 0x0001 Yes Set GPO command 0x80 0x81 Yes Use GPO No Yes No ...

Page 237: ...operty 0x3100 Set AM_CHANNEL_FILTER property 0x3102 Set Soft Mute Settings property 0x3300 3303 CHIP STATE RECEIVING AM SW LW Query AM_TUNE_STATUS command 0x42 Set Volume property 0x4000 Set Mute Unmute property 0x4001 Set AM Tune Frequency command 0x40 ...

Page 238: ...S SCAN AM SW LW Band For valid channels Store valid channels In the Host Yes No Yes No LOOP until reaches End of AM band or Back to the original Channel SEEK next Valid channel Set SEEK settings property 0x3400 3404 SEND AM_SEEK_START COMMAND 0X41 Yes No Set SEEK settings property 0x3400 3404 SEND AM_SEEK_START COMMAND 0X41 CHIP STATE RECEIVING AM SW LW CHIP STATE RECEIVING AM SW LW ...

Page 239: ...e or Weather Band command 0x01 CHIP STATE POWER UP FM Receive or Weather Band Look at FM Receive or Weather Band Flowchart No RECEIVE AM SW LW DONE Yes Send POWER_DOWN command 0x11 CHIP STATE POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in AM SW LW Receive ...

Page 240: ...AM SW LW Receiver Action Data Description Powerup in digital mode CMD ARG1 ARG2 STATUS 0x01 0xC1 0xB0 0x80 POWER_UP Set to AM SW LW Receive Enable interrupts Set to Digital Audio Output Reply Status Clear to send high Action Ensure that DCLK and DFS are already supplied CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x01 0x04 0xBB 0x80 0x80 SET_PROPERTY DIGITAL_OUTPUT_SAMPLE_R...

Page 241: ... high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x01 0x7E 0xF4 0x80 SET_PROPERTY REFCLK_FREQ REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x02 0x02 0x01 0x90 0x80 SET_PROPERTY REFCLK_PRESCALE Divide by 400 example RCLK 13 MHz REFCLK 32500 Hz Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 ...

Page 242: ...ROPERTY AM_RSQ_SNR_HIGH_THRESHOLD 10 dB 0x0A Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x32 0x02 0x00 0x0A 0x80 SET_PROPERTY AM_RSQ_SNR_LOW_THRESHOLD 10 dB 0x0A Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x32 0x03 0x00 0x1E 0x80 SET_PROPERTY AM_RSQ_RSSI_HIGH_THRESHOLD 30 dBµV 0x1E Rep...

Page 243: ... 0x09 0x80 SET_PROPERTY AM_SOFT_MUTE_SNR_THRESHOLD 9 dB 0x09 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x34 0x00 0x02 0x08 0x80 SET_PROPERTY AM_SEEK_BAND_BOTTOM 520 kHz 0x0208 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x34 0x01 0x06 0xAE 0x80 SET_PROPERTY AM_SEEK_BAND_TOP 1710 kHz 0x...

Page 244: ...lear to send high CMD STATUS 0x14 0x81 GET_INT_STATUS Reply Status Clear to send high STCINT 1 CMD ARG1 STATUS 0x41 0x0C 0x80 AM_SEEK_START Seek up and wrap at band boundary Reply Status Clear to send high CMD STATUS 0x14 0x81 GET_INT_STATUS Reply Status Clear to send high STCINT 1 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 0x42 0x01 0x80 0x01 0x03 0xE8 0x2A 0x1A 0x0D 0x95 AM_TUNE_S...

Page 245: ... Figure 16 and the timing parameters for each command are shown in Table 43 CMD ARG1 STATUS RESP1 RESP2 RESP3 RESP4 RESP5 0x43 0x01 0x80 0x00 0x01 0x00 0x2A 0x1A AM_RSQ_STATUS Clear STC interrupt Reply Status Clear to send high No SNR high low RSSI high or low interrupts Channel is valid soft mute is not activated and AFC is not railed RSSI 0x2A 42d 42 dBµV SNR 0x1A 26d 26 dB CMD STATUS 0x11 0x80 ...

Page 246: ... DOWN CHIP STATE POWER UP Power Up With Patch Check Chip Library ID POWER_UP with FUNC 15 command 0x01 POWER UP command 0x01 Library ID Compatible w patch POWER_UP With Patch bit enabled command 0x01 Send Patch Data command 0x15 0x16 Yes No Yes No Check Chip FW Comp rev GET_REV command 0x10 Chip FW Comp Rev are correct Contact Silabs For verification No Yes Contact Silabs For verification ...

Page 247: ...47 Set WB Tune Frequency command 0x50 CHIP STATE RECEIVING WB Set RCLK settings property 0x0201 0x0202 Use Interrupt Use all default Settings Yes No No Set INT settings property 0x0001 Yes Set GPO command 0x80 0x81 Yes Use GPO No ...

Page 248: ...property 0x5108 Set WB Tune Frequency command 0x50 CHIP STATE RECEIVING WB Query WB_TUNE_STATUS command 0x52 Set Volume property 0x4000 Set Mute Unmute property 0x4001 Set WB Valid SNR Threshold property 0x5403 Set WB Valid RSSI Threshold property 0x5404 ...

Page 249: ...o something based on WB_RSQ_STATUS Yes No Monitor Alert Tone ASQ Set ASQ int source property 0x5600 Query WB_ASQ_STATUS command 0x55 Optional Do something based on WB_ASQ_STATUS Yes No Monitor SAME Set SAME int source property 0x5500 Query WB_SAME_STATUS command 0x54 Optional Do something based on WB_SAME_STATUS Yes No Comlete Message Received No Yes ...

Page 250: ...or AM or FM Receive command 0x01 CHIP STATE POWER UP AM or FM Receive Look at AM or FM Receive Flowchart No RECEIVE WB DONE Yes Send POWER_DOWN command 0x11 CHIP STATE POWER DOWN Repeat any of the instructions above after POWER_UP state To change settings No Go back to the very first POWER DOWN state to POWER UP the chip in WB Receive ...

Page 251: ...5 0x80 POWER_UP Set to weatherband receive Enable interrupts Set to Analog Out Reply Status Clear to send high CMD STATUS RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 0x10 0x80 0x25 0x30 0x41 0x13 0x36 0x30 0x41 0x42 GET_REV Reply Status Clear to send high Part Number HEX 0x25 37 dec Si4737 Firmware Major Rev ASCII 0x30 0 Firmware Minor Rev ASCII 0x41 A Patch ID MSB example only Patch ID LSB ex...

Page 252: ...RG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x54 0x04 0x00 0x14 0x80 SET_PROPERTY WB_VALID_RSSI_THRESHOLD Threshold 20 dBµV 0x0014 Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5 PROPD STATUS 0x12 0x00 0x56 0x00 0x00 0x01 0x80 SET_PROPERTY WB_ASQ_INTERRUPT_SOURCE Interrupt when alert tone is present Reply Status Clear to send high CMD ARG1 ARG2 PROP ARG3 PROP ARG4 PROPD ARG5...

Page 253: ...RESP1 RESP2 RESP3 RESP4 RESP5 RESP6 RESP7 RESP8 RESP9 RESP10 RESP11 RESP12 0x54 0x01 0x00 0x80 0x0F 0x00 0xFE 0xFF 0x2D 0x57 0x58 0x52 0x2D 0x56 0x4F 0x57 WB_SAME_STATUS Clear SAME interrupt Begin reading message from byte 0 Reply Status Clear to send high Message flags set State End of message Message length 254 bytes Data confidence level high Data0 Data1 Data2 Data3 Data4 Data5 Data6 Data7 Note...

Page 254: ...erformance RDS Receiver support Added Si4707 WB SAME Receiver support Added Si4740 41 multipath blend and AGC properties Added Si4749 High Performance RDS Receiver support Updated Firmware Library and Component Compatibility tables Added Command Timing Parameters for the WB Receiver Updated FM Transmitter maximum audio volume recommendations ...

Page 255: ...AN332 Confidential Rev 0 2 255 NOTES ...

Page 256: ...lity for the functioning of undescribed features or parameters Silicon Laboratories reserves the right to make changes without further notice Silicon Laboratories makes no warranty rep resentation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and sp...

Reviews:

No comments

Related manuals for Si4700

Brand: u-blox Pages: 25

Brand: Biostar Pages: 53

Brand: Safran Pages: 26

Brand: NXP Semiconductors Pages: 14

Brand: DTK Pages: 50

Brand: Renesas Pages: 20

Brand: ST Pages: 82

Brand: MSI Pages: 91

Brand: Infineon Pages: 30

Brand: ASROCK Pages: 2

Brand: TYAN Pages: 47

Brand: Huawei Pages: 21

Brand: Suzuki Pages: 50

Brand: Intel Pages: 78

Brand: Caen RFID Pages: 29

Brand: Nexcom Pages: 35

Brand: Nexcom Pages: 52

970A-G43 Series

Brand: MSI Pages: 192

Brands by name

0 1 2 3 4 5 6 7 8 9 A B C D E F G H I J K L M N O P Q R S T U V W X Y Z

Popular brands

Load more brands