AN332
Confidential Rev. 0.2
171
6.2. 3-Wire Control Interface Mode
Figures 7 and 8 show the 3-wire Control Interface Read and Write Timing Parameters and Diagrams, respectively.
Refer to the Si471x data sheet for timing parameter values.
Figure 7. 3-Wire Control Interface Write Timing Parameters
Figure 8. 3-Wire Control Interface Read Timing Parameters
3-wire bus mode uses the SCLK, SDIO and SEN pins. A transaction begins when the system controller drives SEN
low. Next, the system controller drives a 9-bit control word on SDIO, which is captured by the device on rising
edges of SCLK. The control word is comprised of a three bit chip address (A7:A5 = 101b), a read/write bit
(write = 0, read = 1), the chip address (A4 = 0), and a four bit register address (A3:A0).
For write operations, the control word is followed by a 16-bit data word, which is captured by the device on rising
edges of SCLK. For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-
around. Next, the device drives the 16-bit read data word serially on SDIO, changing the state of SDIO on each
rising edge of SCLK.
For read operations, the control word is followed by a delay of one-half SCLK cycle for bus turn-around. Next, the
device drives the 16-bit read data word serially on SDIO, changing the state of SDIO on each rising edge of SCLK.
A transaction ends when the system controller sets SEN = 1, then pulses SCLK high and low one final time. SCLK
may either stop or continue to toggle while SEN is high. In 3-wire mode, commands are sent by first writing each
argument to register(s) 0xA1–0xA3, then writing the command word to register 0xA0. A response is retrieved by
reading registers 0xA8–0xAF.
SCLK
70%
30%
SEN
70%
30%
SDIO
A7
A0
70%
30%
t
S
t
S
t
HSDIO
t
HSEN
A6-A5,
R/W,
A4-A1
Address In
Data In
D15
D14-D1
D0
t
HIGH
t
LOW
½ Cycle Bus
Turnaround
SCLK
70%
30%
SEN
70%
30%
SDIO
80%
20%
t
HSDIO
t
CDV
t
CDZ
Address In
Data Out
A7
A0
A6-A5,
R/W,
A4-A1
D15
D14-D1
D0
t
S
t
S
t
HSEN
