Silicon Laboratories EMBER EM358 series, Reference Manual, Page: 80 / 257

EM358x
80 Rev. 0.4
8.3 SPI - Master Mode
The SPI master controller has the following features:

Full duplex operation

Programmable clock frequency (12 MHz max.)

Programmable clock polarity and phase

Selectable data shift direction (either LSB or MSB first)

Receive and transmit FIFOs

Receive and transmit DMA channels
8.3.1 GPIO Usage
The SPI master controller uses the three signals:

MOSI (Master Out, Slave In) – outputs serial data from the master

MISO (Master In, Slave Out) – inputs serial data from a slave

SCLK (Serial Clock) – outputs the serial clock used by MOSI and MISO
The GPIO pins used for these signals are shown in Table 8-3. Additional outputs may be needed to drive the
nSSEL signals on slave devices.
Table 8-3. SPI Master GPIO Usage
MOSI MISO SCLK
Direction
Output Input Output
GPIO Configuration
Alternate Output
(push-pull)
Input Alternate Output
(push-pull)
SC1 pin
PB1 PB2 PB3
SC2 pin
PA0 PA1 PA2
8.3.2 Set Up and Configuration
Both serial controllers, SC1 and SC2, support SPI master mode. SPI master mode is enabled by the following
register settings:

The serial controller mode register (SCx_MODE) is 2.

The SC_SPIMST bit in the SPI configuration register (SCx_SPICFG) is 1.
The SPI serial clock (SCLK) is produced by a programmable clock generator. The serial clock is produced by
dividing down 12 MHz according to this equation:
EXP LIN
MHz
rate
2 * ) 1 (
12


EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the SCx_RATELIN register.
EXP and LIN can both be zero so the SPI master mode clock may be 12 Mbps.
The SPI master controller supports various frame formats depending upon the clock polarity (SC_SPIPOL), clock
phase (SC_SPIPHA), and direction of data (SC_SPIORD) (see Table 8-4). The bits SC_SPIPOL, SC_SPIPHA,
and SC_SPIORD are defined within the SCx_SPICFG register.