Silicon Laboratories EMBER EM358 series, Reference Manual, Page: 225 / 257

EM358x
Rev. 0.4 225
Table 11-4 shows the options for ADC sample times and the significant bits in the conversion results.
Table 11-4. ADC Sample Times
ADC_PERIOD Sample
Clocks
Sample Time (µs) Sample Frequency (kHz)
Significant Bits
1 MHz clock 6 MHz clock 1 MHz clock 6 MHz clock
0 32 32 5.33 31.3 188 7
1 64 64 10.7 15.6 93.8 8
2 128 128 21.3 7.81 46.9 9
3 256 256 42.7 3.91 23.4 10
4 512 512 85.3 1.95 11.7 11
5 1024 1024 170 0.977 5.86 12
6 2048 2048 341 0.488 2.93 13
7 4096 4096 682 0.244 1.47 14
Note:
ADC sample timing is the same whether the EM358x is using the 24 MHz crystal oscillator or the 12 MHz
high-speed RC oscillator. This facilitates using the ADC soon after the CPU wakes from deep sleep, before
switching to the crystal oscillator.
11.2 Interrupts
The ADC has its own top-level interrupt in the NVIC. The ADC interrupt is enabled by writing the INT_ADC bit to
the INT_CFGSET register, and cleared by writing the INT_ADC bit to the INT_CFGCLR register. Chapter 3,
Interrupt System, describes the interrupt system in detail.
Five kinds of ADC events can generate an ADC interrupt, and each has a bit flag in the INT_ADCFLAG register to
identify the reason(s) for the interrupt:

INT_ADCOVF – an ADC conversion result was ready but the DMA was disabled (DMA buffer overflow).

INT_ADCSAT– the gain correction multiplication exceeded the limits for a signed 16-bit number (gain
saturation).
 INT_ADCULDFULL – the DMA wrote to the last location in the buffer (DMA buffer full).
 INT_ADCULDHALF – the DMA wrote to the last location of the first half of the DMA buffer (DMA buffer half
full).

INT_ADCDATA – there is data ready in the ADC_DATA register.
Bits in INT_ADCFLAG register may be cleared by writing a 1 to their position. Writing 0 to any bit in the
INT_ADCFLAG register is ineffectual.
The INT_ADCCFG register controls whether or not INT_ADCFLAG register bits actually propagate the ADC
interrupt to the NVIC. Only the events whose bits are 1 in the INT_ADCCFG register can do so.
For non-interrupt (polled) ADC operation set the INT_ADCCFG register to zero, and read the bit flags in the
INT_ADCFLAG register to determine the ADC status.
Note:
When making changes to the ADC configuration it is best to disable the DMA beforehand. If this isn’t done
it can be difficult to determine at which point the sampled data in the DMA buffer switched from the old
configuration to the new configuration. However, since the ADC will be left running, if it completes a
conversion after the DMA is disabled, the INT_ADCOVF flag will be set. To prevent these unwanted DMA
buffer overflow indications, clear the INT_ADCOVF flag immediately after enabling the DMA, preferably
with interrupts off. Disabling the ADC in addition to the DMA is often undesirable because of the additional
analog startup time when it is re-enabled.