EM358x
170
Rev. 0.4
Figure 10-6. Counter Timing Diagram, Update Event when TIM_ARBE = 1 (TIMx_ARR buffered)
10.3.2.2 Down-Counting Mode
In down-counting mode, the counter counts from the auto-reload value (contents of the TIMx_ARR register) down
to 0, then restarts from the auto-reload value and generates a counter underflow event.
A UEV can be generated at each counter underflow, by setting the TIM_UG bit in the TIMx_EGR register, or by
using the slave mode controller. Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1
register, to avoid updating the shadow registers while writing new values in the buffer registers. No UEV occurs
until the TIM_UDIS bit is written to 0. However, the counter restarts from the current auto-reload value, whereas
the prescaler’s counter restarts from 0, but the prescale rate doesn’t change.
In addition, if the TIM_URS bit in the TIMx_CR1 register is set, setting the TIM_UG bit generates a UEV, but
without setting the INT_TIMUIF flag. Thus no interrupt request is sent. This avoids generating both update and
capture interrupts when clearing the counter on the capture event.
When a UEV occurs, the update flag (the INT_TIMUIF bit in the INT_TIMxFLAG register) is set (unless TIM_URS
is 1) and the following registers are updated:
The prescaler shadow register is reloaded with the buffer value (contents of the TIMx_PSC register).
The auto-reload active register is updated with the buffer value (contents of the TIMx_ARR register). The auto-
reload is updated before the counter is reloaded, so that the next period is the expected one.
Figure 10-7 and Figure 10-8 show some examples of the counter behavior for different clock frequencies when
TIMx_ARR = 0x36.
Figure 10-7. Counter Timing Diagram, Internal Clock Divided by 1
Summary of Contents for EMBER EM358 series
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