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Silicon Laboratories EMBER EM358 series Reference Manual Download Page 55

EM358x 

 

 

Rev. 0.4 

55 

 

Note:  

Disabling all debug functionality prevents external debug tools from operating, including flash programming 

and high-level debug tools. 

Disabling the entire SWJ debugger interface is accomplished by setting the GPIO_DEBUGDIS bit in the 

GPIO_DBGCFG register and not having GPIO PC4 configured in SWDIO mode. In this configuration all 

debugger-related pins (PC0, PC2, PC3, PC4) behave as standard GPIOs. 
Disabling only the JTAG debugger interface is accomplished by setting the GPIO_DEBUGDIS bit and configuring 

PC4 in SWDIO mode. When GPIO_DEBUGDIS is set and GPIO PC4 is in SWDIO mode, JTAG debugger-related 

pins (PC0, PC2, PC3) behave as standard GPIOs. Note that allowing the PC4 GPIO to operate as SWDIO does 

not affect the internal debug state of the chip. 
If the SWJ debugger interface is already active (in either mode), the bit GPIO_DEBUGDIS cannot be set. When 

GPIO_DEBUGDIS is set, the SWJ debugger interface can be reclaimed by activating the SWJ while the EM358x 

is held in reset. If the SWJ debugger interface is forced active in this manner, the bit GPIO_FORCEDBG is set in 

the GPIO_DBGSTAT register. The SWJ debugger interface is defined as active when the CDBGPWRUPREQ 

signal, a bit in the debug port’s CRTL/STAT register in the SWJ, is set high by an external debug tool. 
If the SWJ debugger interface is active, and switched into Serial Wire mode (by the external debugger), then the 

JTAG only pins (PC0, PC2, PC3) behave as standard GPIOs. The use of SWDIO mode for GPIO PC4 allows 

reclaiming the JTAG only pins when an external debugger is not used. 

7.4  Reset 

A full chip reset is one due to power on (low or high voltage), the nRESET pin, the watchdog, or the 

SYSRESETREQ bit. A full chip reset affects the GPIO configuration as follows: 

 

The GPIO_PxCFGH/L configurations of all pins are configured as floating inputs.  

 

The GPIO_EXTREGEN bit is set in the GPIO_DBGCFG register, which overrides the normal configuration for 

PA7. 

 

The GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is cleared, allowing Serial Wire/JTAG access to 

override the normal configuration of PC0, PC2, PC3, and PC4. 

7.5  Boot Configuration 

nBOOTMODE is a special alternate function of PA5 that is active only during a pin reset (nRESET) or a power-

on-reset of the always-powered domain (POR HV). If nBOOTMODE is asserted (pulled or driven low) when 

coming out of reset, the processor starts executing an embedded serial-link-only monitor instead of its normal 

program. 
While in reset and during the subsequent power-on-reset startup delay (512 OSCHF clocks), PA5 is automatically 

configured as an input with a pull-up resistor. At the end of this time, the EM358x samples nBOOTMODE: a high 

level selects normal boot mode, and a low level selects the embedded monitor. Figure 7-2 shows the timing 

parameters for invoking monitor mode from a pin (nRESET) reset. Because OSCHF is running uncalibrated 

during the reset sequence, the time for 512 OSCHF clocks may vary as indicated. 

Summary of Contents for EMBER EM358 series

Page 1: ... specifications are subject to change without notice EMBER EM358X REFERENCE MANUAL This reference manual accompanies several documents to provide the complete description of Ember EM358x devices In the event that the device data sheet and this document contain conflicting information the device data sheet should be considered the authoritative source ...

Page 2: ...EM358x 2 Rev 0 4 ...

Page 3: ... 17 2 2 3 Registers 17 2 3 Memory Protection Unit 18 3 Interrupt System 19 3 1 Nested Vectored Interrupt Controller NVIC 19 3 2 Event Manager 22 3 3 Non maskable Interrupt NMI 24 3 4 Faults 25 3 5 Registers 26 4 Radio Module 33 4 1 Receive Rx Path 33 4 1 1 Rx Baseband 33 4 1 2 RSSI and CCA 34 4 2 Transmit Tx Path 34 4 2 1 Tx Baseband 34 4 2 2 TX_ACTIVE and nTX_ACTIVE Signals 34 4 3 Calibration 34 ...

Page 4: ...rs 49 5 6 Security Accelerator 50 6 Integrated Voltage Regulator 51 7 GPIO General Purpose Input Output 52 7 1 GPIO Ports 52 7 2 Configuration 53 7 3 Forced Functions 54 7 4 Reset 55 7 5 Boot Configuration 55 7 6 GPIO Modes 56 7 6 1 Analog Mode 56 7 6 2 Input Mode 56 7 6 3 SWDIO Mode 57 7 6 4 Output Mode 57 7 6 5 Alternate Output Mode 57 7 6 6 Alternate Output SPI Slave MISO Mode 57 7 7 Wake Monit...

Page 5: ...6 6 Interrupts 100 8 6 7 Registers 102 8 7 DMA Channels 106 8 7 1 Registers 107 9 USB Device 124 9 1 Overview 124 9 2 Host Drivers 124 9 3 References 124 9 4 GPIO Usage and USB Pin Assignments 124 9 5 Application Schematics 125 9 6 Endpoints 125 9 7 Buffers and DMA 126 9 8 Set Up and Configuration 126 9 9 DMA Usage and Transfers 128 9 10 Enumeration 128 9 11 Normal COM Port Operation 128 9 12 Susp...

Page 6: ...0 4 Interrupts 167 10 5 Registers 168 11 ADC Analog to Digital Converter 195 11 1 Setup and Configuration 195 11 1 1 GPIO Usage 196 11 1 2 Voltage Reference 196 11 1 3 Offset Gain Correction 196 11 1 4 DMA 196 11 1 5 ADC Configuration Register 197 11 2 Interrupts 199 11 3 Operation 200 11 4 Calibration 200 11 5 ADC Key Parameters 201 11 6 Registers 206 12 Trace Port Interface Unit TPIU 218 13 Inst...

Page 7: ...EM358x Rev 0 4 7 ...

Page 8: ...hort range wireless standard enabling connectivity for a broad range of electronic devices Version 2 1 EDR Enhanced Data Rate can be found here http www bluetooth org docman handlers downloaddoc ashx doc_id 241363 1 1 6 IEEE 802 15 4 2003 This standard defines the protocol and compatible interconnection for data communication devices using low data rate low power and low complexity short range rad...

Page 9: ... AES encryption CCM Improved Counter with CBC MAC Mode for AES encryption CIB Customer Information Block CLK1K 1 kHz Clock CLK32K 32 768 kHz Crystal Clock CPU Central Processing Unit CRC Cyclic Redundancy Check CSMA CA Carrier Sense Multiple Access Collision Avoidance CTR Counter Mode CTS Clear to Send DNL Differential Non Linearity DMA Direct Memory Access DWT Data Watchpoint and Trace EEPROM Ele...

Page 10: ...ast significant bit MAC Medium Access Control MFB Main Flash Block MISO Master in slave out MOS Metal Oxide Semiconductor P channel or N channel MOSI Master out slave in MPU Memory Protection Unit MSB Most significant bit MSL Moisture Sensitivity Level NACK Negative Acknowledge NIST National Institute of Standards and Technology NMI Non Maskable Interrupt NVIC Nested Vectored Interrupt Controller ...

Page 11: ...cy RMS Root Mean Square RoHS Restriction of Hazardous Substances RSSI Receive Signal Strength Indicator RTS Request to Send Rx Receive SYSCLK System clock SDFR Spurious Free Dynamic Range SFD Start Frame Delimiter SINAD Signal to noise and distortion ratio SPI Serial Peripheral Interface SWJ Serial Wire and JTAG Interface THD Total Harmonic Distortion TRNG True random number generator TWI Two Wire...

Page 12: ...s The ARM CortexTM M3 clock speed is configurable to 6 MHz 12 MHz or 24 MHz For normal operation 24 MHz is preferred over 12 MHz due to improved performance for all applications and improved duty cycling for applications using sleep modes The 6 MHz operation can only be used when radio operations are not required since the radio requires an accurate 12 MHz clock The ARM CortexTM M3 in the EM358x h...

Page 13: ...EM358x Rev 0 4 13 2 2 Embedded Memory Figure 2 1 shows the EM358x ARM CortexTM M3 memory map Figure 2 1 EM358x ARM CortexTM M3 Memory Map ...

Page 14: ...ss 0x08000000 since this address mapping is always available in all modes The MFB stores all program instructions and constant data A small portion of the MFB is devoted to non volatile token storage using the Ember Simulated EEPROM system 2 2 1 3 Fixed Information Block The 2 kB FIB is used to store fixed manufacturing data including serial numbers and calibration values The start of the FIB is m...

Page 15: ...state 0xFF enable read protection when coming out of reset The internal state of read protection active versus disabled can only be changed by applying a full chip reset If a debugger is connected to the EM358x the intrusion state is latched Read protection is combined with this latched intrusion signal When both read protection and intrusion are set all flash is disconnected from the internal bus...

Page 16: ... 6 Write protection of address range 0x08038000 0x0803BFFF bit 7 Write protection of address range 0x0803C000 0x0803FFFF Option Byte 6 bit 0 Write protection of address range 0x08040000 0x08043FFF bit 1 Write protection of address range 0x08044000 0x08047FFF bit 2 Write protection of address range 0x08048000 0x0804BFFF bit 3 Write protection of address range 0x0804C000 0x0804FFFF bit 4 Write prote...

Page 17: ... channels in total See Chapter 8 Section 8 7 and Chapter 11 Section 11 1 4 for a description of how to configure the serial controllers and ADC for DMA operation The DMA channels do not use AHB system bus bandwidth as they access the RAM directly The EM358x integrates a DMA arbiter that ensures fair access to the microprocessor as well as the peripherals through a fixed priority scheme appropriate...

Page 18: ...figures the MPU in a standard configuration and application software should not modify it The configuration is designed for optimal detection of illegal instruction or data accesses If an illegal access is attempted the MPU captures information about the access type the address being accessed and the location of the offending software This simplifies software debugging and increases the reliabilit...

Page 19: ...nterrupts it contains 18 individually vectored peripheral interrupts specific to the EM358x The NVIC defines a list of exceptions These exceptions include not only traditional peripheral interrupts but also more specialized events such as faults and CPU reset In the ARM CortexTM M3 NVIC a CPU reset event is considered an exception of the highest priority and the stack pointer is loaded from the fi...

Page 20: ...l interrupt MAC Receive 26 MAC Receive peripheral interrupt ADC 27 ADC peripheral interrupt IRQA 28 IRQA peripheral interrupt IRQB 29 IRQB peripheral interrupt IRQC 30 IRQC peripheral interrupt IRQD 31 IRQD peripheral interrupt Debug 32 Debug peripheral interrupt 33 Reserved 34 Reserved USB 35 USB peripheral interrupt where applicable The NVIC also contains a software configurable interrupt priori...

Page 21: ...mple latch INT_CFGSET and INT_CFGCLR set and clear a mask on the output of the latch Interrupts may be pended and cleared at any time but any pended interrupt will not be taken unless the corresponding mask INT_CFGSET is set which allows that interrupt to propagate If an INT_CFGSET bit is set and the corresponding INT_PENDSET bit is set then the interrupt will propagate and be taken If INT_CFGSET ...

Page 22: ...terrupts Writing 1 to a bit in the INT_periphCFG register enables the second level interrupt Writing 0 to a bit in the INT_periphCFG register disables it The INT_periphCFG register behaves like a mask and is responsible for allowing the INT_periphFLAG bits to propagate into the top level NVIC interrupts INT_periphFLAG indicates second level interrupts that have occurred Writing 1 to a bit in a INT...

Page 23: ...e 3 2 NVIC and EM Peripheral Interrupt Map NVIC Interrupt top level EM Interrupt second level NVIC Interrupt top level EM Interrupt second level 19 INT_USB INT_USBFLAG Register 6 INT_SC2 INT_SC2FLAG register 23 INT_USBWAKEUP 12 INT_SCTXULDB 22 INT_USBRESUME 11 INT_SCTXULDA 21 INT_USBSUSPEND 10 INT_SCRXULDB 20 INT_USBRESET 9 INT_SCRXULDA 19 INT_USBSOF 8 INT_SCNAK 18 INT_USBNAK 7 INT_SCCDMFIN 17 INT...

Page 24: ...able interrupt NMI is a special case Despite being one of the 10 standard ARM CortexTM M3 NVIC interrupts it is sourced from the Event Manager like a peripheral interrupt The NMI has two second level sources failure of the 24 MHz crystal and watchdog low water mark 1 Failure of the 24MHz crystal If the EM358x s main clock SYSCLK is operating from the 24 MHz crystal and the crystal fails the EM358x...

Page 25: ...es are made precise faults The four bus faults are WRONGSIZE Generated by an 8 bit or 16 bit read or write of an APB peripheral register This fault can also result from an unaligned 32 bit access PROTECTED Generated by a user mode unprivileged write to a system APB or AHB peripheral or protected RAM see Chapter 2 Section 2 2 2 3 RESERVED Generated by a read or write to an address within an APB per...

Page 26: ...RQB 13 RW Write 1 to enable IRQB interrupt Writing 0 has no effect INT_IRQA 12 RW Write 1 to enable IRQA interrupt Writing 0 has no effect INT_ADC 11 RW Write 1 to enable ADC interrupt Writing 0 has no effect INT_MACRX 10 RW Write 1 to enable MAC receive interrupt Writing 0 has no effect INT_MACTX 9 RW Write 1 to enable MAC transmit interrupt Writing 0 has no effect INT_MACTMR 8 RW Write 1 to enab...

Page 27: ...rite 1 to disable IRQB interrupt Writing 0 has no effect INT_IRQA 12 RW Write 1 to disable IRQA interrupt Writing 0 has no effect INT_ADC 11 RW Write 1 to disable ADC interrupt Writing 0 has no effect INT_MACRX 10 RW Write 1 to disable MAC receive interrupt Writing 0 has no effect INT_MACTX 9 RW Write 1 to disable MAC transmit interrupt Writing 0 has no effect INT_MACTMR 8 RW Write 1 to disable MA...

Page 28: ...RQB 13 RW Write 1 to pend IRQB interrupt Writing 0 has no effect INT_IRQA 12 RW Write 1 to pend IRQA interrupt Writing 0 has no effect INT_ADC 11 RW Write 1 to pend ADC interrupt Writing 0 has no effect INT_MACRX 10 RW Write 1 to pend MAC receive interrupt Writing 0 has no effect INT_MACTX 9 RW Write 1 to pend MAC transmit interrupt Writing 0 has no effect INT_MACTMR 8 RW Write 1 to pend MAC timer...

Page 29: ... Write 1 to unpend IRQB interrupt Writing 0 has no effect INT_IRQA 12 RW Write 1 to unpend IRQA interrupt Writing 0 has no effect INT_ADC 11 RW Write 1 to unpend ADC interrupt Writing 0 has no effect INT_MACRX 10 RW Write 1 to unpend MAC receive interrupt Writing 0 has no effect INT_MACTX 9 RW Write 1 to unpend MAC transmit interrupt Writing 0 has no effect INT_MACTMR 8 RW Write 1 to unpend MAC ti...

Page 30: ...INT_RSVD17 17 RW Reserved this bit should be ignored INT_DEBUG 16 R Debug interrupt active INT_IRQD 15 R IRQD interrupt active INT_IRQC 14 R IRQC interrupt active INT_IRQB 13 R IRQB interrupt active INT_IRQA 12 R IRQA interrupt active INT_ADC 11 R ADC interrupt active INT_MACRX 10 R MAC receive interrupt active INT_MACTX 9 R MAC transmit interrupt active INT_MACTMR 8 R MAC timer interrupt active I...

Page 31: ...18 RW Reserved this bit should be ignored INT_RSVD17 17 RW Reserved this bit should be ignored INT_MISSIRQD 15 RW IRQD interrupt missed INT_MISSIRQC 14 RW IRQC interrupt missed INT_MISSIRQB 13 RW IRQB interrupt missed INT_MISSIRQA 12 RW IRQA interrupt missed INT_MISSADC 11 RW ADC interrupt missed INT_MISSMACRX 10 RW MAC receive interrupt missed INT_MISSMACTX 9 RW MAC transmit interrupt missed INT_...

Page 32: ... 16 bit read or write of an APB peripheral register This fault can also result from an unaligned 32 bit access PROTECTED 2 RW A bus fault resulted from a user mode unprivileged write to a system APB or AHB peripheral or protected RAM RESERVED 1 RW A bus fault resulted from a read or write to an address within an APB peripheral s 4 kB block range but above the last physical register in that block C...

Page 33: ... of the Rx path both to enable the reception of small and large wanted signals and to tolerate large interferers 4 1 1 Rx Baseband The EM358x Rx digital baseband implements a coherent demodulator for optimal performance The baseband demodulates the O QPSK signal at the chip level and synchronizes with the IEEE 802 15 4 2003 defined preamble An automatic gain control AGC module adjusts the analog g...

Page 34: ... the radio using dedicated hardware resources 4 4 Integrated MAC Module The EM358x integrates most of the IEEE 802 15 4 2003 MAC requirements in hardware This allows the ARM CortexTM M3 CPU to provide greater bandwidth to application and network operations In addition the hardware acts as a first line filter for unwanted packets The EM358x MAC uses a DMA interface to RAM to further reduce the over...

Page 35: ...ules without affecting their normal operation It cannot be used to inject packets into the PHY MAC interface This 500 kbps asynchronous interface comprises the frame signal PTI_EN PA4 and the data signal PTI_DATA PA5 PTI is supported by the Ember development tools 4 6 Random Number Generator Thermal noise in the analog circuitry is digitized to provide entropy for a true random number generator TR...

Page 36: ...2K OSC32A OSC32B JRST always on domain PORESET SYSRESET DAPRESET mem domain ARM Cortex M3 Debug AHB AP SYSRESETREQ core domain ARM Cortex M3 CPU FLITF option byte error Flash RAM OSC24M OSCHF OSCA OSCB clock switch SYSCLK CDBGRSTREQ Power Management Watchdog Sleep Timer watchdog deep sleep wakeup REG_EN recomended connections for internal regulator PRESETHV PRESETLV registers registers Security Ac...

Page 37: ...regulator output and supply requires a connection between both VDD_CORE pins 5 1 2 Externally regulated power Optionally the on chip regulators may be left unused and the core and memory domains may instead be powered from external supplies The nominal supply voltages of the internal power domains must be respected that is core and RAM at nominally 1 25 V and flash at nominally 1 8 V A regulator e...

Page 38: ...nd generates the pin reset source nRESET to the Reset Generation module Table 5 4 contains the specification for the filter Table 5 4 Reset Filter Specification for nRESET Parameter Min Typ Max Unit Reset filter time constant 2 1 12 0 16 0 µs Reset pulse width to guarantee a reset 26 0 µs Reset pulse width guaranteed not to cause a reset 0 1 0 µs 5 2 1 3 Watchdog Reset The EM358x contains a watchd...

Page 39: ...rated a restart to the system The reset conditions recorded are POR HV always on domain power supply failure POR LV core domain POR LVcore or memory domain POR LVmem power supply failure nRESET pin reset asserted watchdog watchdog timer expired SYSRESETREQ software reset by SYSERSETREQ from ARM CortexTM M3 CPU deep sleep wakeup wake up from deep sleep option byte error error check failed when read...

Page 40: ...X X X X X POR LV due to waking from normal deep sleep X X X X POR LV not due to waking from normal deep sleep X X X X X nRESET X X X X Watchdog X X X SYSRESETREQ X X X Option byte error X X X Normal deep sleep X X X X Emulated deep sleep X X Debug reset X 5 3 Clocks The EM358 integrates four oscillators 12 MHz RC oscillator 24 MHz crystal oscillator 10 kHz RC oscillator 32 768 kHz crystal oscillat...

Page 41: ...ev 0 4 41 Figure 5 2 shows a block diagram of the clocks in the EM358x This simplified view shows all the clock sources and the general areas of the chip to which they are routed Figure 5 2 Clocks Block Diagram ...

Page 42: ...1 7 V 5 5 3 2 High Frequency Crystal Oscillator OSC24M The high frequency crystal oscillator OSC24M requires an external 24 MHz crystal with an accuracy of 40 ppm Based upon the application s bill of materials and current consumption requirements the external crystal may cover a range of ESR requirements Table 5 7 contains the specification for the high frequency crystal oscillator The crystal osc...

Page 43: ...thout re calibration 1 Temperature dependence Frequency variation with temperature for a change from 40o C to 85o C without re calibration 2 5 3 4 Low Frequency Crystal Oscillator OSC32K A low frequency 32 768 kHz crystal oscillator OSC32K is provided as an optional timing reference for on chip timers This oscillator is designed for use with an external watch crystal When using the 32 768 kHz crys...

Page 44: ...urther automatic control is invoked by hardware when flash programming is enabled To ensure accuracy of the flash controller s timers the FCLK frequency is forced to 12 MHz during flash programming and erase operations Table 5 10 System Clock Modes OSC24M_CTRL_OSC24M_SEL CPU_CLKSEL_FIELD SYSCLK PCLK FCLK Flash Program Erase Inactive Flash Program Erase Active 0 OSCHF 0 Normal CPU 12 MHz 6 MHz 6 MH...

Page 45: ... into an idle state where execution is suspended until any interrupt occurs All power domains remain fully powered and nothing is reset Deep Sleep 1 The primary deep sleep state In this state the core power domain is fully powered down and the sleep timer is active Deep Sleep 2 The same as Deep Sleep 1 except that the sleep timer is inactive to save power In this mode the sleep timer cannot wake u...

Page 46: ... port in the SWJ The following sources are only available in deep sleep 1 since the sleep timer is not active in deep sleep 2 Wake on sleep timer compare A Wake on sleep timer compare B Wake on sleep timer wrap The following source is only available in deep sleep 0 since the SWJ is required to write a memory mapped register to set this wake source and the SWJ only has access to some registers in d...

Page 47: ... the Idle Sleeping state Deep sleep is achieved by executing a WFI instruction with the SLEEPDEEP bit in SCS_SCR set This triggers the state transitions around the main loop of the diagram resulting in powering down the EM358x s core logic and leaving only the always on domain powered Wake up is triggered when one of the pre determined events occurs If a deep sleep is requested the EM358x first en...

Page 48: ...n the SWJ is set and the EM358x will only enter deep sleep 0 the Emulated Deep Sleep state The CDBGPWRUPREQ bit indicates that a debug tool is logically connected to the chip and therefore debug state may be in the system debug components To maintain the debug state in the system debug components only deep sleep 0 may be used since deep sleep 0 will not cause a power cycle or reset of the core dom...

Page 49: ...option for 0x2000B000 to 0x2000BFFF RETAIN 10 RW Sets the retention option for 0x2000A000 to 0x2000AFFF RETAIN 9 RW Sets the retention option for 0x20009000 to 0x20009FFF RETAIN 8 RW Sets the retention option for 0x20008000 to 0x20008FFF RETAIN 7 RW Sets the retention option for 0x20007000 to 0x20007FFF RETAIN 6 RW Sets the retention option for 0x20006000 to 0x20006FFF RETAIN 5 RW Sets the retenti...

Page 50: ...W Reserved this bit can change during normal operation When writing to PERIPHERAL_DISABLE the value of this bit must be preserved PERIDIS_ADC 4 RW Disable the clock to the ADC peripheral PERIDIS_TIM2 3 RW Disable the clock to the TIM2 peripheral PERIDIS_TIM1 2 RW Disable the clock to the TIM1 peripheral PERIDIS_SC1 1 RW Disable the clock to the SC1 peripheral PERIDIS_SC2 0 RW Disable the clock to ...

Page 51: ...t after initialization 1V8 regulator output after reset 5 1 75 5 Regulator output after reset 1V25 regulator output 5 1 25 5 V Regulator output after initialization 1V25 regulator output after reset 5 1 45 5 Regulator output after reset 1V8 regulator capacitor 2 2 µF Low ESR tantalum capacitor ESR greater than 2 Ω ESR less than 10 Ω de coupling less than 100 nF ceramic 1V25 regulator capacitor 1 0...

Page 52: ...n analog mode disconnects the digital input from the pin and applies a high logic level to the input of the Schmitt trigger Only one device at a time can control a GPIO output The output is controlled in normal output mode by the GPIO_PxOUT register and in alternate output mode by a peripheral device When in input mode or analog mode digital output is disabled 7 1 GPIO Ports The 24 GPIO pins are g...

Page 53: ...loating input only for retaining SWDIO functionality of PC4 when the GPIO_DEBUGDIS bit in the GPIO_DBGCFG register is set Input pull up or pull down 0x8 Digital input with an internal pull up or pull down A set bit in GPIO_PxOUT selects pull up and a cleared bit selects pull down Output is disabled Output push pull 0x1 Push pull output GPIO_PxOUT controls the output Output open drain 0x5 Open drai...

Page 54: ...Mode Forced Signal PA7 Open drain output REG_EN PC0 Input with pull up JRST PC2 Push pull output JTDO PC3 Input with pull up JDTI PC41 Input with pull up JTMS PC41 Bidirectional push pull output or floating input controlled by debugger interface SWDIO 1 The choice of PC4 s forced signal is normally controlled by an external debug tool JTMS is forced when the SWJ is in JTAG mode and SWDIO is forced...

Page 55: ...e by the external debugger then the JTAG only pins PC0 PC2 PC3 behave as standard GPIOs The use of SWDIO mode for GPIO PC4 allows reclaiming the JTAG only pins when an external debugger is not used 7 4 Reset A full chip reset is one due to power on low or high voltage the nRESET pin the watchdog or the SYSRESETREQ bit A full chip reset affects the GPIO configuration as follows The GPIO_PxCFGH L co...

Page 56: ...log Mode Analog mode enables analog functions and disconnects a pin from the digital input and output logic Only the following GPIO pins have analog functions PA0 and PA1 can be the differential IO pins for the USB device PA4 PA5 PB5 PB6 PB7 and PC1 can be analog inputs to the ADC PB0 can be an external analog voltage reference input to the ADC or it can output the internal analog voltage referenc...

Page 57: ...e 0 activates the N MOS current sink 1 tri states the pin In push pull mode 0 activates the N MOS current sink 1 activates the P MOS current source The internal pull up and pull down resistors are disabled The Schmitt trigger input is connected to the pin Reading GPIO_PxIN returns the input at the pin Reading GPIO_PxOUT returns the last value written to the register Note Depending on configuration...

Page 58: ...n the WAKE_SEL register must be set Waking up from GPIO activity does not work with pins configured for analog mode since the digital logic input is always set to 1 when in analog mode Refer to Chapter 5 System Modules for information on the EM358x s power management and sleep modes 7 8 External Interrupts The EM358x can use up to four external interrupt sources IRQA IRQB IRQC and IRQD each with i...

Page 59: ... PC6 7 PA7 15 PB7 23 PC7 In some cases it may be useful to assign IRQC or IRQD to an input also in use by a peripheral for example to generate an interrupt from the slave select signal nSSEL in an SPI slave mode interface Refer to Chapter 3 Interrupt System for further information regarding the EM358x interrupt system 7 9 Debug Control and Status Two GPIO registers are largely concerned with debug...

Page 60: ...SC1RXD Standard PB3 TIM2C3 4 SC1SCLK TIM2C3 4 SC1SCLK SC1nCTS Standard PB4 TIM2C4 4 SC1nRTS TIM2C4 4 SC1nSSEL Standard PB5 ADC0 TIM2CLK TIM1MSK Standard PB6 ADC1 TIM1C1 TIM1C1 IRQB High PB7 ADC2 TIM1C2 TIM1C2 High PC0 TRACEDATA1 JRST 5 High PC1 ADC3 TRACEDATA3 Standard PC2 JTDO 6 SWO TRACEDATA0 Standard PC3 TRACECLK JTDI 5 Standard PC4 SWDIO 7 SWDIO 7 JTMS 7 Standard PC5 TX_ACTIVE Standard PC6 OSC...

Page 61: ...ntrol 0x0 Analog input or output GPIO_PxIN always reads 1 0x1 Output push pull GPIO_PxOUT controls the output 0x4 Input floating 0x5 Output open drain GPIO_PxOUT controls the output 0x6 SWDIO bidirectional only for retaining SWDIO functionality of PC4 when the GPIO_DEBUGDIS bit of the GPIO_DBGCFG register is set 0x8 Input pulled up or down selected by GPIO_PxOUT 0 pull down 1 pull up 0x9 Alternate...

Page 62: ...0x0 Analog input or output GPIO_PxIN always reads 1 0x1 Output push pull GPIO_PxOUT controls the output 0x4 Input floating 0x5 Output open drain GPIO_PxOUT controls the output 0x6 SWDIO bidirectional only for retaining SWDIO functionality of PC4 when the GPIO_DEBUGDIS bit of the GPIO_DBGCFG register is set 0x8 Input pulled up or down selected by GPIO_PxOUT 0 pull down 1 pull up 0x9 Alternate outpu...

Page 63: ...ail description 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0 Bitname Bitfield Access Description Px7 7 RW Input level at pin Px7 Px6 6 RW Input level at pin Px6 Px5 5 RW Input level at pin Px5 Px4 4 RW Input level at pin Px4 Px3 3 RW Input level at pin Px3 Px2 2 RW Input level a...

Page 64: ...he following detail description 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0 Bitname Bitfield Access Description Px7 7 RW Output data for Px7 Px6 6 RW Output data for Px6 Px5 5 RW Output data for Px5 Px4 4 RW Output data for Px4 Px3 3 RW Output data for Px3 Px2 2 RW Output data ...

Page 65: ...x1 Px0 Bitname Bitfield Access Description Px7 7 W Write 1 to clear the output data bit for Px7 writing 0 has no effect Px6 6 W Write 1 to clear the output data bit for Px6 writing 0 has no effect Px5 5 W Write 1 to clear the output data bit for Px5 writing 0 has no effect Px4 4 W Write 1 to clear the output data bit for Px4 writing 0 has no effect Px3 3 W Write 1 to clear the output data bit for ...

Page 66: ...ccess Description GPIO_PXSETRSVD 15 8 W Reserved these bits must be set to 0 Px7 7 W Write 1 to set the output data bit for Px7 writing 0 has no effect Px6 6 W Write 1 to set the output data bit for Px6 writing 0 has no effect Px5 5 W Write 1 to set the output data bit for Px5 writing 0 has no effect Px4 4 W Write 1 to set the output data bit for Px4 writing 0 has no effect Px3 3 W Write 1 to set ...

Page 67: ... 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 Px7 Px6 Px5 Px4 Px3 Px2 Px1 Px0 Bitname Bitfield Access Description Px7 7 RW Write 1 to enable wakeup monitoring of Px7 Px6 6 RW Write 1 to enable wakeup monitoring of Px6 Px5 5 RW Write 1 to enable wakeup monitoring of Px5 Px4 4 RW Write 1 to enable wakeup monitoring of Px4 Px3 3 RW Write 1 to enable wakeup monitoring...

Page 68: ... 6 5 4 3 2 1 0 0 0 0 0 IRQD_WAKE_FILTER SC2_WAKE_FILTER SC1_WAKE_FILTER GPIO_WAKE_FILTER Bitname Bitfield Access Description IRQD_WAKE_FILTER 3 RW Enable filter on GPIO wakeup source IRQD SC2_WAKE_FILTER 2 RW Enable filter on GPIO wakeup source SC2 PA2 SC1_WAKE_FILTER 1 RW Enable filter on GPIO wakeup source SC1 PB2 GPIO_WAKE_FILTER 0 RW Enable filter on GPIO wakeup sources enabled by the GPIO_PnW...

Page 69: ...26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 SEL_GPIO Bitname Bitfield Access Description SEL_GPIO 4 0 RW Pin assigned to IRQx 0x00 PA0 0x01 PA1 0x02 PA2 0x03 PA3 0x04 PA4 0x05 PA5 0x06 PA6 0x07 PA7 0x08 PB0 0x09 PB1 0x0A PB2 0x0B PB3 0x0C PB4 0x0D PB5 0x0E PB6 0x0F PB7 0x10 PC0 0x11 PC1 0x12 PC2 0x13 PC3 0x14 PC4 0x15...

Page 70: ...0 Substitute A B C or D for x in the following detail description 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 GPIO_INTFILT 7 6 5 4 3 2 1 0 GPIO_INTMOD 0 0 0 0 0 Bitname Bitfield Access Description GPIO_INTFILT 8 RW Set this bit to enable digital filtering on IRQx GPIO_INTMOD 7 5 RW IRQx triggering mode 0x0 Disabled 0x1 Rising ...

Page 71: ...FLAG INT_IRQBFLAG INT_IRQAFLAG Bitname Bitfield Access Description INT_IRQDFLAG 3 RW IRQD interrupt pending Write 1 to clear IRQD interrupt writing 0 has no effect INT_IRQCFLAG 2 RW IRQC interrupt pending Write 1 to clear IRQC interrupt writing 0 has no effect INT_IRQBFLAG 1 RW IRQB interrupt pending Write 1 to clear IRQB interrupt writing 0 has no effect INT_IRQAFLAG 0 RW IRQA interrupt pending W...

Page 72: ...iption GPIO_DEBUGDIS 5 RW Disable debug interface override of normal GPIO configuration Configuring PC4 in SWDIO mode will retain the Serial Wire SWDIO functionality 0 Permit debug interface to be active 1 Disable debug interface if it is not already active GPIO_EXTREGEN 4 RW Enable REG_EN override of PA7 s normal GPIO configuration 0 Disable override 1 Enable override GPIO_DBGCFGRSVD 3 RW Reserve...

Page 73: ...GPIO_FORCEDBG GPIO_SWEN Bitname Bitfield Access Description GPIO_BOOTMODE 3 R The state of the nBOOTMODE signal sampled at the end of reset 0 nBOOTMODE was not asserted it read high 1 nBOOTMODE was asserted it read low GPIO_FORCEDBG 1 R Status of debugger interface 0 Debugger interface not forced active 1 Debugger interface forced active by debugger cable GPIO_SWEN 0 R Status of Serial Wire interf...

Page 74: ...SPI and UART modes Receive and transmit FIFOs allow faster data speeds using byte at a time interrupts For the highest SPI and UART speeds dedicated receive and transmit DMA channels reduce CPU loading and extend the allowable time to service a serial controller interrupt Polled operation is also possible using direct access to the serial data registers Figure 8 1 shows the components of the seria...

Page 75: ...or UART to the SCx_MODE register Table 8 1 SC1 GPIO Usage and Configuration PB1 PB2 PB3 PB4 SPI Master SC1MOSI Alternate Output push pull SC1MISO Input SC1SCLK Alternate Output push pull not used SPI Slave SC1MISO Alternate Output push pull SPI Slave MISO Mode SC1MOSI Input SC1SCLK Input SC1nSSEL Input TWI Master SC1SDA Alternate Output open drain SC1SCL Alternate Output open drain not used not us...

Page 76: ...gister Address 0x4000C054 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 SC_MODE Bitname Bitfield Access Description SC_MODE 1 0 RW Serial controller mode 0 Disabled 1 UART mode valid only for SC1 2 SPI mode 3 TWI mode ...

Page 77: ...r received UART interrupt pending INT_SCTXULDB 12 RW DMA transmit buffer B unloaded interrupt pending INT_SCTXULDA 11 RW DMA transmit buffer A unloaded interrupt pending INT_SCRXULDB 10 RW DMA receive buffer B unloaded interrupt pending INT_SCRXULDA 9 RW DMA receive buffer A unloaded interrupt pending INT_SCNAK 8 RW NACK received TWI interrupt pending INT_SCCMDFIN 7 RW START STOP command complete ...

Page 78: ... RW Frame error received UART interrupt enable INT_SCTXULDB 12 RW DMA transmit buffer B unloaded interrupt enable INT_SCTXULDA 11 RW DMA transmit buffer A unloaded interrupt enable INT_SCRXULDB 10 RW DMA receive buffer B unloaded interrupt enable INT_SCRXULDA 9 RW DMA receive buffer A unloaded interrupt enable INT_SCNAK 8 RW NACK received TWI interrupt enable INT_SCCMDFIN 7 RW START STOP command c...

Page 79: ...21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 SC_TXIDLELEVEL SC_TXFREELEVEL SC_RXVALLEVEL Bitname Bitfield Access Description SC_TXIDLELEVEL 2 RW Transmitter idle interrupt mode 0 edge triggered 1 level triggered SC_TXFREELEVEL 1 RW Transmit buffer free interrupt mode 0 edge triggered 1 level triggered SC_RXVALLEVEL 0 RW Receive buffer has data i...

Page 80: ...ion Alternate Output push pull Input Alternate Output push pull SC1 pin PB1 PB2 PB3 SC2 pin PA0 PA1 PA2 8 3 2 Set Up and Configuration Both serial controllers SC1 and SC2 support SPI master mode SPI master mode is enabled by the following register settings The serial controller mode register SCx_MODE is 2 The SC_SPIMST bit in the SPI configuration register SCx_SPICFG is 1 The SPI serial clock SCLK...

Page 81: ... SC_SPITXFREE bit in the SCx_SPISTAT register When the transmit FIFO empties and the last character has been shifted out the SC_SPITXIDLE bit in the SCx_SPISTAT register is set Characters received are stored in the receive FIFO Receiving characters sets the SC_SPIRXVAL bit in the SCx_SPISTAT register indicating that characters can be read from the receive FIFO Characters received while the receive...

Page 82: ...ler second level interrupts are generated by the following events Transmit FIFO empty and last character shifted out depending on SCx_INTMODE either the 0 to 1 transition or the high level of SC_SPITXIDLE Transmit FIFO changed from full to not full depending on SCx_INTMODE either the 0 to 1 transition or the high level of SC_SPITXFREE Receive FIFO changed from empty to not empty depending on SCx_I...

Page 83: ... 7 6 5 4 3 2 1 0 SC_DATA Bitname Bitfield Access Description SC_DATA 7 0 RW Transmit and receive data register Writing to this register adds a byte to the transmit FIFO Reading from this register takes the next byte from the receive FIFO and clears the overrun error bit if it was set In UART mode SC1 only reading from this register loads the UART status register with the parity and frame error sta...

Page 84: ...r sending this busy token are transmit buffer underrun condition when using DMA in master or slave mode empty FIFO in slave mode and the busy token will always be sent as the first byte every time nSSEL is asserted while operating in slave mode Clear this bit to send the BUSY token 0xFF and set this bit to repeat the last byte Changes to this bit take effect when the transmit FIFO is empty and the...

Page 85: ...0 SC_SPITXIDLE SC_SPITXFREE SC_SPIRXVAL SC_SPIRXOVF Bitname Bitfield Access Description SC_SPITXIDLE 3 R This bit is set when both the transmit FIFO and the transmit serializer are empty SC_SPITXFREE 2 R This bit is set when the transmit FIFO has space to accept at least one byte SC_SPIRXVAL 1 R This bit is set when the receive FIFO contains at least one byte SC_SPIRXOVF 0 R This bit is set if a b...

Page 86: ...ear Prescaler Register Address 0x4000C060 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 SC_RATELIN Bitname Bitfield Access Description SC_RATELIN 3 0 RW The linear component LIN of the clock rate in the equation rate 12MHz LIN 1 2 EXP ...

Page 87: ...ntial Prescaler Register Address 0x4000C064 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 SC_RATEEXP Bitname Bitfield Access Description SC_RATEEXP 3 0 RW The exponential component EXP of the clock rate in the equation rate 12MHz LIN 1 2 EXP ...

Page 88: ...SEL Slave Select enables serial communication with the slave The GPIO pins that can be assigned to these signals are shown in Table 8 5 Table 8 5 SPI Slave GPIO Usage MOSI MISO SCLK nSSEL Direction Input Output Input Input GPIO Configuration Input Alternate Output push pull SPI Slave MISO Mode Input Input SC1 pin PB2 PB1 PB3 PB4 SC2 pin PA0 PA1 PA2 PA3 8 4 2 Set Up and Configuration Both serial co...

Page 89: ...hen the MISO pin is configured as Alternate Output push pull SPI Slave MISO Mode A falling edge on nSSEL resets the SPI slave shift registers Characters transmitted and received by the SPI slave controller are buffered in the transmit and receive FIFOs that are both 4 entries deep When software writes a character to the SCx_DATA register it is pushed onto the transmit FIFO Similarly when software ...

Page 90: ...re and use the serial receive and transmit DMA channels When using the receive DMA channel and nSSEL transitions to the high deasserted state the active buffer s receive DMA count register SCx_RXCNTA B is saved in the SCx_RXCNTSAVED register SCx_RXCNTSAVED is only written the first time nSSEL goes high after a buffer has been loaded Subsequent rising edges set a status bit but are otherwise ignore...

Page 91: ...is produced by a programmable clock generator SCL is produced by dividing down 12 MHz according to this equation EXP LIN MHz rate 2 1 12 EXP is the value written to the SCx_RATEEXP register and LIN is the value written to the SCx_RATELIN register Table 8 8 shows the rate settings for Standard Mode TWI 100 kbps and Fast Mode TWI 400 kbps operation Table 8 8 TWI Clock Rate Programming Clock Rate SCx...

Page 92: ... SCLout 0 0 0 0 No pending frame segment 1 1 1 1 1 1 1 1 Illegal 1 The notation xxx means that the corresponding column header below is inserted to form the field name Full TWI frames have to be constructed by software from individual TWI segments All necessary segment transitions are shown in Figure 8 2 ACK or NACK generation of a TWI receive frame segment is determined with the SC_TWIACK bit in ...

Page 93: ...t until the bit is clear Alternatively the SC_TWITXFIN bit in the SCx_TWISTAT register can be used for waiting To initiate a receive segment set the SC_TWIRECV bit in the SCx_TWICTRL1 register wait until it is clear and then read from the SCx_DATA register Alternatively the SC_TWIRXFIN bit in the SCx_TWISTAT register can be used for waiting Now the SC_TWIRXNAK bit in the SCx_TWISTAT register indic...

Page 94: ...0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 SC_TWICMDFIN SC_TWIRXFIN SC_TWITXFIN SC_TWIRXNAK Bitname Bitfield Access Description SC_TWICMDFIN 3 R This bit is set when a START or STOP command completes It clears on the next TWI bus activity SC_TWIRXFIN 2 R This bit is set when a byte is received It clears on the next TWI bus activity SC_TWITXFIN 1 R This bit is set when a by...

Page 95: ... 6 5 4 3 2 1 0 0 0 0 0 SC_TWISTOP SC_TWISTART SC_TWISEND SC_TWIRECV Bitname Bitfield Access Description SC_TWISTOP 3 RW Setting this bit sends the STOP command It clears when the command completes SC_TWISTART 2 RW Setting this bit sends the START or repeated START command It clears when the command completes SC_TWISEND 1 RW Setting this bit transmits a byte It clears when the command completes SC_...

Page 96: ...ess 0x4000C050 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SC_TWIACK Bitname Bitfield Access Description SC_TWIACK 0 RW Setting this bit signals ACK after a received byte Clearing this bit signals NACK after a received byte ...

Page 97: ...M358x is able to receive data nCTS Clear To Send inhibits sending data from the EM358x if not asserted The GPIO pins assigned to these signals are shown in Table 8 10 Table 8 10 UART GPIO Usage TXD RXD nCTS1 nRTS1 Direction Output Input Input Output GPIO Configuration Alternate Output push pull Input Input Alternate Output push pull SC1 pin PB1 PB2 PB3 PB4 1 only used if RTS CTS hardware flow cont...

Page 98: ...rrors may occur when Ferror baud Tgap 6 10 where Tgap inter byte gap in seconds baud baud rate in bps Ferror relative frequency error in ppm For example if the baud rate tolerance between receive and transmit is 200 ppm reasonable if both sides are derived from a crystal and the baud rate is 115200 bps then errors will not occur until the inter byte gap exceeds 43 ms If the gap is exceeded then th...

Page 99: ... characters When idle serial data TXD or RXD is held in the high state Serial data transitions to the low state in the start bit at the beginning of a character frame Figure 8 3 UART Character Frame Format 8 6 3 FIFOs Characters transmitted and received by the UART are buffered in the transmit and receive FIFOs that are both 4 entries deep see Figure 8 4 When software writes a character to the SC1...

Page 100: ...dware control of nRTS nRTS is asserted if room for at least 2 characters in receive FIFO 1 The notation xxx means that the corresponding column header below is inserted to form the field name 8 6 5 DMA The DMA Channels section describes how to configure and use the serial receive and transmit DMA channels The receive DMA channel has special provisions to record UART receive errors When the DMA cha...

Page 101: ...B Receive DMA buffer A B complete 1 to 0 transition of SC_RXACTA B Character received with parity error Character received with frame error Character received and lost when receive FIFO was full receive overrun error To enable CPU interrupts set the desired interrupt bits in the second level INT_SCxCFG register and enable the top level SCx interrupt in the NVIC by writing the INT_SCx bit in the IN...

Page 102: ...a register is read and is cleared if the receive FIFO is empty SC_UARTFRMERR 4 R This bit is set when the byte in the data register was received with a frame error This bit is updated when the data register is read and is cleared if the receive FIFO is empty SC_UARTRXOVF 3 R This bit is set when the receive FIFO has been overrun This occurs if a byte is received when the receive FIFO is full This ...

Page 103: ... SC_UARTFLOW 5 RW Set this bit to enable using nRTS nCTS flow control signals Clear this bit to disable the signals When this bit is clear the UART transmitter will not be inhibited by nCTS SC_UARTODD 4 RW If parity is enabled specifies the kind of parity 0 Even parity 1 Odd parity SC_UARTPAR 3 RW Specifies whether to use parity bits 0 Don t use parity 1 Use parity SC_UART2STP 2 RW Number of stop ...

Page 104: ...68 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_UARTPER 7 6 5 4 3 2 1 0 SC_UARTPER Bitname Bitfield Access Description SC_UARTPER 15 0 RW The integer part of baud rate period N in the equation rate 24MHz 2 N F ...

Page 105: ...et 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 0 SC_UARTFRAC Bitname Bitfield Access Description SC_UARTFRAC 0 RW The fractional part of the baud rate period F in the equation rate 24MHz 2 N F ...

Page 106: ...gister Enable top level NVIC interrupts by setting the INT_SCx bit in the INT_CFGSET register Start the DMA by loading the DMA buffers by setting the SC_TXLODA B or SC_RXLODA B bits in the SCx_DMACTRL register A DMA buffer s end address SCx_TXENDA B or SCx_RXENDA B can be written while the buffer is loaded or active This is useful for receiving messages that contain an initial byte count since it ...

Page 107: ...W Setting this bit loads DMA transmit buffer A addresses and allows the DMA controller to start processing transmit buffer A If both buffer A and B are loaded simultaneously buffer A will be used first This bit is cleared when DMA completes Writing a zero to this bit has no effect Reading this bit returns DMA buffer status 0 DMA processing is complete or idle 1 DMA processing is active or pending ...

Page 108: ... frame error from the receive FIFO It is cleared the next time buffer B is loaded or when the receive DMA is reset SC1 in UART mode only SC_RXFRMA 8 R This bit is set when DMA receive buffer A reads a byte with a frame error from the receive FIFO It is cleared the next time buffer A is loaded or when the receive DMA is reset SC1 in UART mode only SC_RXPARB 7 R This bit is set when DMA receive buff...

Page 109: ...was the next buffer to load and when it drained the FIFO the overrun error was passed up to the DMA and flagged with this bit Cleared the next time buffer A is loaded and when the receive DMA is reset SC_TXACTB 3 R This bit is set when DMA transmit buffer B is active SC_TXACTA 2 R This bit is set when DMA transmit buffer A is active SC_RXACTB 1 R This bit is set when DMA receive buffer B is active...

Page 110: ...0 SC2_TXBEGA Transmit DMA Begin Address Register A Address 0x4000C010 Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_TXBEGA 7 6 5 4 3 2 1 0 SC_TXBEGA Bitname Bitfield Access Description SC_TXBEGA 15 0 RW DMA transmit buffer A start address ...

Page 111: ...0 SC2_TXBEGB Transmit DMA Begin Address Register B Address 0x4000C018 Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_TXBEGB 7 6 5 4 3 2 1 0 SC_TXBEGB Bitname Bitfield Access Description SC_TXBEGB 15 0 RW DMA transmit buffer B start address ...

Page 112: ...it DMA End Address Register A Address 0x4000C014 Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_TXENDA 7 6 5 4 3 2 1 0 SC_TXENDA Bitname Bitfield Access Description SC_TXENDA 15 0 RW Address of the last byte that will be read from the DMA transmit buffer A ...

Page 113: ...it DMA End Address Register B Address 0x4000C01C Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_TXENDB 7 6 5 4 3 2 1 0 SC_TXENDB Bitname Bitfield Access Description SC_TXENDB 15 0 RW Address of the last byte that will be read from the DMA transmit buffer B ...

Page 114: ...1 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_TXCNT 7 6 5 4 3 2 1 0 SC_TXCNT Bitname Bitfield Access Description SC_TXCNT 15 0 R The offset from the start of the active DMA transmit buffer from which the next byte will be read This register is set to zero when the buffer is loaded and when the DMA is reset ...

Page 115: ...00 SC2_RXBEGA Receive DMA Begin Address Register A Address 0x4000C000 Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_RXBEGA 7 6 5 4 3 2 1 0 SC_RXBEGA Bitname Bitfield Access Description SC_RXBEGA 15 0 RW DMA receive buffer A start address ...

Page 116: ...00 SC2_RXBEGB Receive DMA Begin Address Register B Address 0x4000C008 Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_RXBEGB 7 6 5 4 3 2 1 0 SC_RXBEGB Bitname Bitfield Access Description SC_RXBEGB 15 0 RW DMA receive buffer B start address ...

Page 117: ...e DMA End Address Register A Address 0x4000C004 Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_RXENDA 7 6 5 4 3 2 1 0 SC_RXENDA Bitname Bitfield Access Description SC_RXENDA 15 0 RW Address of the last byte that will be written in the DMA receive buffer A ...

Page 118: ...e DMA End Address Register B Address 0x4000C00C Reset 0x20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_RXENDB 7 6 5 4 3 2 1 0 SC_RXENDB Bitname Bitfield Access Description SC_RXENDB 15 0 RW Address of the last byte that will be written in the DMA receive buffer B ...

Page 119: ... 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_RXCNTA 7 6 5 4 3 2 1 0 SC_RXCNTA Bitname Bitfield Access Description SC_RXCNTA 15 0 RW The offset from the start of DMA receive buffer A at which the next byte will be written This register is set to zero when the buffer is loaded and when the DMA is reset If this register is written when the buffer is not loaded the buffer is l...

Page 120: ... 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_RXCNTB 7 6 5 4 3 2 1 0 SC_RXCNTB Bitname Bitfield Access Description SC_RXCNTB 15 0 RW The offset from the start of DMA receive buffer B at which the next byte will be written This register is set to zero when the buffer is loaded and when the DMA is reset If this register is written when the buffer is not loaded the buffer is l...

Page 121: ...ister Address 0x4000C070 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 SC_RXCNTSAVED 7 6 5 4 3 2 1 0 SC_RXCNTSAVED Bitname Bitfield Access Description SC_RXCNTSAVED 15 0 R Receive DMA count saved in SPI slave mode when nSSEL deasserts The count is only saved the first time nSSEL deasserts ...

Page 122: ...C_RXERRA 7 6 5 4 3 2 1 0 SC_RXERRA Bitname Bitfield Access Description SC_RXERRA 15 0 R The offset from the start of DMA receive buffer A of the first byte received with a parity frame or overflow error Note that an overflow error occurs at the input to the receive FIFO so this offset is 4 bytes before the overflow position If there is no error it reads zero This register will not be updated by su...

Page 123: ...C_RXERRB 7 6 5 4 3 2 1 0 SC_RXERRB Bitname Bitfield Access Description SC_RXERRB 15 0 R The offset from the start of DMA receive buffer B of the first byte received with a parity frame or overflow error Note that an overflow error occurs at the input to the receive FIFO so this offset is 4 bytes before the overflow position If there is no error it reads zero This register will not be updated by su...

Page 124: ...a PC without needing a physical UART RS 232 but still use the basic application serial functionality that has been available on a UART There are two options for host drivers The Silicon Labs supplied driver There is an EM358VPInstaller available for both x64 and x86 Windows The device driver is signed and certified by Microsoft Windows Hardware Compatibility The Windows PC USB built in driver Sili...

Page 125: ...so the device knows when the USB is physically connected or not connected This VBUS monitoring ability is needed for software to control the pull up resistor appropriately since the USB specification requires that the pull up resistor is disconnected if VBUS is not connected PA3 is a logical choice for VBUS monitoring since SC2 won t be available due to USB being on PA0 and PA1 If PA3 is used one ...

Page 126: ...done in the endpoint descriptor Each endpoint can be enabled independently except endpoint 0 which is always enabled All endpoints have both an IN device to host or TX and OUT host to device or RX direction These function as independent endpoints and can be enabled independently In USB parlance the IN OUT pair is a logical endpoint whilst the individual endpoints are physical endpoints Physical en...

Page 127: ...d buffer B if necessary There are two registers to allow positioning of the A and B buffers independently in RAM Register USB_BUFBASEA is for positioning buffer A and register USB_BUFBASEB is for positioning buffer B when double buffering is enabled Note 8 byte alignment is the only requirement as to where the buffer can be located in RAM 9 9 Standard Commands A set of USB standard commands are de...

Page 128: ...face Interface None Set interface and alternate setting to use Set Address Device None Set the device address for the interface Clear Feature Device None Clear a device feature The only valid features are DEVICE_REMOTE_WAKEUP and TEST_MOD as defined in the USB specification Set Feature Device None Set a device feature The only valid features are DEVICE_REMOTE_WAKEUP and TEST_MOD as defined in the ...

Page 129: ...host can inspect and control this feature This remote wakeup choice must also be indicated in the device descriptor reported to the host when the device enumerates When beginning to enable interrupts it s always best to start with clearing any possible stale interrupt flags This is done by writing a 1 to every bit in the INT_USBFLAG register The register INT_USBCFG is used for configuring the USB ...

Page 130: ...opriate USB_TXLOADEPxy bit in the USB_TXLOAD register A buffer should not be modified while the USB_TXLOADxy bit is still set Modifying a buffer s RAM before the buffer has unloaded could result in incorrect data being transferred Setting the register USB_TXBUFSIZEEPxy to 0 to transmit a zero length packet is valid and in this situation the data in buffer s RAM does not matter Because the interrup...

Page 131: ... been in idle sleep with the slower clock mode With respect to current consumption in the larger system INT_USBWAKEUP can be treated like INT_USBRESUME with respect to using pieces of the system that consume higher current such as the radio 9 13 Interrupts USB interrupts are generated on the following events INT_USBRXVALIDEPx Reception becoming valid is indicated with the INT_USBRXVALIDEPx bits Th...

Page 132: ...6B 22 RW Set this bit to enable endpoint 6 buffer B OUT USB_ENBUFOUTEP5B 21 RW Set this bit to enable endpoint 5 buffer B OUT USB_ENBUFOUTEP4B 20 RW Set this bit to enable endpoint 4 buffer B OUT USB_ENBUFOUTEP3B 19 RW Set this bit to enable endpoint 3 buffer B OUT USB_ENBUFOUTEP2B 18 RW Set this bit to enable endpoint 2 buffer B OUT USB_ENBUFOUTEP1B 17 RW Set this bit to enable endpoint 1 buffer ...

Page 133: ...l commands Instead this bit is a means of indicating to the host that ClearFeature EP0 is acknowledged or unexpected USB_SELFPWRD 0 RW Set this bit to indicate whether USB is self powered The state of this register is reflected in the data returned from a GetStatus Device standard command handled by the USB core The device descriptor returned to the host during enumeration must match the self powe...

Page 134: ... 5 4 3 2 1 0 USB_TIMESTAMP Bitname Bitfield Access Description USB_RESETSTAT 12 R This bit is set while USB reset is active The rising edge of the reset status generates the INT_USBRESET interrupt USB_SUSPENDED 11 R This bit is set while the device is suspended The rising of edge of the suspended status generates the INT_USBSUSPEND interrupt USB_TIMESTAMP 10 0 R The timestamp of the reception of t...

Page 135: ... USB_ENABLEINEP 0 Bitname Bitfield Access Description USB_ENABLEINEP6 6 RW Set this bit to enable endpoint 6 buffer A IN USB_ENABLEINEP5 5 RW Set this bit to enable endpoint 5 buffer A IN USB_ENABLEINEP4 4 RW Set this bit to enable endpoint 4 buffer A IN USB_ENABLEINEP3 3 RW Set this bit to enable endpoint 3 buffer A IN USB_ENABLEINEP2 2 RW Set this bit to enable endpoint 2 buffer A IN USB_ENABLEI...

Page 136: ...B_ENABLEOU TEP0 Bitname Bitfield Access Description USB_ENABLEOUTEP6 6 RW Set this bit to enable endpoint 6 buffer A OUT USB_ENABLEOUTEP5 5 RW Set this bit to enable endpoint 5 buffer A OUT USB_ENABLEOUTEP4 4 RW Set this bit to enable endpoint 4 buffer A OUT USB_ENABLEOUTEP3 3 RW Set this bit to enable endpoint 3 buffer A OUT USB_ENABLEOUTEP2 2 RW Set this bit to enable endpoint 2 buffer A OUT USB...

Page 137: ... 31 RW Set this bit to enable endpoints to be associated with Interface 1 Clear this bit to keep endpoints only associated with Interface 0 USB_INTF1SELEP6 6 RW Set this bit to associate endpoint 6 IN with Interface 1 USB_INTF1SELEP5 5 RW Set this bit to associate endpoint 5 IN with Interface 1 USB_INTF1SELEP4 4 RW Set this bit to associate endpoint 4 IN with Interface 1 USB_INTF1SELEP3 3 RW Set t...

Page 138: ...Address 0x40011004 Reset 0x20000000 31 30 29 28 27 26 25 24 USB_BUFBASEy_FIELD 23 22 21 20 19 18 17 16 USB_BUFBASEy_FIELD 15 14 13 12 11 10 9 8 USB_BUFBASEy_FIELD 7 6 5 4 3 2 1 0 USB_BUFBASEy_FIELD Bitname Bitfield Access Description USB_BUFBASEy_FIELD 31 0 RW Write this register with a RAM address to position buffer y in RAM 8 byte alignment is the only requirement as to where the buffer can be l...

Page 139: ...bit to load endpoint 3 buffer B for transmit Auto clears to 0 USB_TXLOADEP2B 10 RW Write this bit to load endpoint 2 buffer B for transmit Auto clears to 0 USB_TXLOADEP1B 9 RW Write this bit to load endpoint 1 buffer B for transmit Auto clears to 0 USB_TXLOADEP0B 8 RW Write this bit to load endpoint 0 buffer B for transmit Auto clears to 0 USB_TXLOADEP6A 6 RW Write this bit to load endpoint 6 buff...

Page 140: ...USB_TXACTIVEEP4B 12 R This bit is set while endpoint 4 buffer B is active USB_TXACTIVEEP3B 11 R This bit is set while endpoint 3 buffer B is active USB_TXACTIVEEP2B 10 R This bit is set while endpoint 2 buffer B is active USB_TXACTIVEEP1B 9 R This bit is set while endpoint 1 buffer B is active USB_TXACTIVEEP0B 8 R This bit is set while endpoint 0 buffer B is active USB_TXACTIVEEP6A 6 R This bit is...

Page 141: ...s to Transmit for Endpoint 0 Buffer B Register Address 0x4001102C Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_TXBUFSIZEEP0y Bitname Bitfield Access Description USB_TXBUFSIZEEP0y 3 0 RW Size in bytes of data to transmit for endpoint 0 buffer y Must be written before TX_LOAD is set and remain unmodified while TX_LOAD is set ...

Page 142: ...s to Transmit for Endpoint 1 Buffer B Register Address 0x40011030 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_TXBUFSIZEEP1y Bitname Bitfield Access Description USB_TXBUFSIZEEP1y 3 0 RW Size in bytes of data to transmit for endpoint 1 buffer y Must be written before TX_LOAD is set and remain unmodified while TX_LOAD is set ...

Page 143: ...s to Transmit for Endpoint 2 Buffer B Register Address 0x40011034 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_TXBUFSIZEEP2y Bitname Bitfield Access Description USB_TXBUFSIZEEP2y 3 0 RW Size in bytes of data to transmit for endpoint 2 buffer y Must be written before TX_LOAD is set and remain unmodified while TX_LOAD is set ...

Page 144: ...s to Transmit for Endpoint 3 Buffer B Register Address 0x40011038 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_TXBUFSIZEEP3y Bitname Bitfield Access Description USB_TXBUFSIZEEP3y 6 0 RW Size in bytes of data to transmit for endpoint 3 buffer y Must be written before TX_LOAD is set and remain unmodified while TX_LOAD is set ...

Page 145: ...s to Transmit for Endpoint 4 Buffer B Register Address 0x4001103C Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_TXBUFSIZEEP4y Bitname Bitfield Access Description USB_TXBUFSIZEEP4y 5 0 RW Size in bytes of data to transmit for endpoint 4 buffer y Must be written before TX_LOAD is set and remain unmodified while TX_LOAD is set ...

Page 146: ...s to Transmit for Endpoint 5 Buffer B Register Address 0x40011040 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_TXBUFSIZEEP5y Bitname Bitfield Access Description USB_TXBUFSIZEEP5y 6 0 RW Size in bytes of data to transmit for endpoint 5 buffer y Must be written before TX_LOAD is set and remain unmodified while TX_LOAD is set ...

Page 147: ...smit for Endpoint 6 Buffer B Register Address 0x40011044 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 USB_TXBUFSIZEEP6y 7 6 5 4 3 2 1 0 USB_TXBUFSIZEEP6y Bitname Bitfield Access Description USB_TXBUFSIZEEP6y 9 0 RW Size in bytes of data to transmit for endpoint 6 buffer y Must be written before TX_LOAD is set and remain unmodified while TX_LOAD is set ...

Page 148: ...B_RXVALIDEP2B 10 RW This bit is set when endpoint 2 buffer B reception is valid USB_RXVALIDEP1B 9 RW This bit is set when endpoint 1 buffer B reception is valid USB_RXVALIDEP0B 8 RW This bit is set when endpoint 0 buffer B reception is valid USB_RXVALIDEP6A 6 RW This bit is set when endpoint 6 buffer A reception is valid USB_RXVALIDEP5A 5 RW This bit is set when endpoint 5 buffer A reception is va...

Page 149: ...ytes Received in Endpoint 0 Buffer B Register Address 0x40011094 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_RXBUFSIZEEP0y Bitname Bitfield Access Description USB_RXBUFSIZEEP0y 3 0 R Size in bytes of data received on endpoint 0 buffer y This register is valid only after the corresponding USB_RXVALIDEP0y bit is set ...

Page 150: ...ytes Received in Endpoint 1 Buffer B Register Address 0x40011098 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_RXBUFSIZEEP1y Bitname Bitfield Access Description USB_RXBUFSIZEEP1y 3 0 RW Size in bytes of data received on endpoint 1 buffer y This register is valid only after the corresponding USB_RXVALIDEP1y bit is set ...

Page 151: ...ytes Received in Endpoint 2 Buffer B Register Address 0x4001109C Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_RXBUFSIZEEP2y Bitname Bitfield Access Description USB_RXBUFSIZEEP2y 3 0 RW Size in bytes of data received on endpoint 2 buffer y This register is valid only after the corresponding USB_RXVALIDEP2y bit is set ...

Page 152: ...ytes Received in Endpoint 3 Buffer B Register Address 0x400110A0 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_RXBUFSIZEEP3y Bitname Bitfield Access Description USB_RXBUFSIZEEP3y 6 0 RW Size in bytes of data received on endpoint 3 buffer y This register is valid only after the corresponding USB_RXVALIDEP3y bit is set ...

Page 153: ...ytes Received in Endpoint 4 Buffer B Register Address 0x400110A4 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_RXBUFSIZEEP4y Bitname Bitfield Access Description USB_RXBUFSIZEEP4y 5 0 RW Size in bytes of data received on endpoint 4 buffer y This register is valid only after the corresponding USB_RXVALIDEP4y bit is set ...

Page 154: ...ytes Received in Endpoint 5 Buffer B Register Address 0x400110A8 Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_RXBUFSIZEEP5y Bitname Bitfield Access Description USB_RXBUFSIZEEP5y 6 0 RW Size in bytes of data received on endpoint 5 buffer y This register is valid only after the corresponding USB_RXVALIDEP5y bit is set ...

Page 155: ...ived in Endpoint 6 Buffer B Register Address 0x400110AC Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 USB_RXBUFSIZEEP6y 7 6 5 4 3 2 1 0 USB_RXBUFSIZEEP6y Bitname Bitfield Access Description USB_RXBUFSIZEEP6y 9 0 RW Size in bytes of data received on endpoint 6 buffer y This register is valid only after the corresponding USB_RXVALIDEP6y bit is set ...

Page 156: ...ite this bit to force clearing of endpoint 4 IN buffer Auto clears to 0 USB_BUFCLRINEP3 3 W Write this bit to force clearing of endpoint 3 IN buffer Auto clears to 0 USB_BUFCLRINEP2 2 W Write this bit to force clearing of endpoint 2 IN buffer Auto clears to 0 USB_BUFCLRINEP1 1 W Write this bit to force clearing of endpoint 1 IN buffer Auto clears to 0 USB_BUFCLRINEP0 0 W Write this bit to force cl...

Page 157: ... RW Write this bit to stall endpoint 6 IN This bit will not auto clear USB_STALLINEP5 5 RW Write this bit to stall endpoint 5 IN This bit will not auto clear USB_STALLINEP4 4 RW Write this bit to stall endpoint 4 IN This bit will not auto clear USB_STALLINEP3 3 RW Write this bit to stall endpoint 3 IN This bit will not auto clear USB_STALLINEP2 2 RW Write this bit to stall endpoint 2 IN This bit w...

Page 158: ...RW Write this bit to stall endpoint 6 OUT This bit will not auto clear USB_STALLOUTEP5 5 RW Write this bit to stall endpoint 5 OUT This bit will not auto clear USB_STALLOUTEP4 4 RW Write this bit to stall endpoint 4 OUT This bit will not auto clear USB_STALLOUTEP3 3 RW Write this bit to stall endpoint 3 OUT This bit will not auto clear USB_STALLOUTEP2 2 RW Write this bit to stall endpoint 2 OUT Th...

Page 159: ... Reset 0x0 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 USB_RESUME Bitname Bitfield Access Description USB_RESUME 0 W Write this bit to resume from the suspended state This activity is also known as remote wakeup Auto clears to 0 ...

Page 160: ...0 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 USB_RXPIPECLR USB_TXPIPECLR Bitname Bitfield Access Description USB_RXPIPECLR 1 R Write this bit to force clearing of the receive DMA pipeline Auto clears to 0 USB_TXPIPECLR 0 R Write this bit to force clearing of the transmit DMA pipeline Auto clears to 0 ...

Page 161: ...ESET INT_USBSOF INT_USBNAK INT_USBPIPER XOVF INT_USBPIPET XUND 15 14 13 12 11 10 9 8 INT_USBBUFR XOVF INT_USBBUFTX UND INT_USBRXVAL IDEP6 INT_USBRXVAL IDEP5 INT_USBRXVAL IDEP4 INT_USBRXVAL IDEP3 INT_USBRXVAL IDEP3 INT_USBRXVAL IDEP1 7 6 5 4 3 2 1 0 INT_USBRXVA LIDEP0 INT_USBTXACT IVEEP6 INT_USBTXACT IVEEP5 INT_USBTXACT IVEEP4 INT_USBTXACT IVEEP3 INT_USBTXACT IVEEP2 INT_USBTXACT IVEEP1 INT_USBTXACT...

Page 162: ... bit pends this interrupt INT_USBRXVALIDEP4 11 RW The rising edge of either USB_RXVALIDEP4y bit pends this interrupt INT_USBRXVALIDEP3 10 RW The rising edge of either USB_RXVALIDEP3y bit pends this interrupt INT_USBRXVALIDEP2 9 RW The rising edge of either USB_RXVALIDEP2y bit pends this interrupt INT_USBRXVALIDEP1 8 RW The rising edge of either USB_RXVALIDEP1y bit pends this interrupt INT_USBRXVAL...

Page 163: ...USBRESET INT_USBSOF INT_USBNAK INT_USBPIPER XOVF INT_USBPIPET XUND 15 14 13 12 11 10 9 8 INT_USBBUFR XOVF INT_USBBUFTX UND INT_USBRXVAL IDEP6 INT_USBRXVAL IDEP5 INT_USBRXVAL IDEP4 INT_USBRXVAL IDEP3 INT_USBRXVAL IDEP3 INT_USBRXVAL IDEP1 7 6 5 4 3 2 1 0 INT_USBRXVA LIDEP0 INT_USBTXACT IVEEP6 INT_USBTXACT IVEEP5 INT_USBTXACT IVEEP4 INT_USBTXACT IVEEP3 INT_USBTXACT IVEEP2 INT_USBTXACT IVEEP1 INT_USBT...

Page 164: ...5y bit interrupt enable INT_USBRXVALIDEP4 11 RW The rising edge of either USB_RXVALIDEP4y bit interrupt enable INT_USBRXVALIDEP3 10 RW The rising edge of either USB_RXVALIDEP3y bit interrupt enable INT_USBRXVALIDEP2 9 RW The rising edge of either USB_RXVALIDEP2y bit interrupt enable INT_USBRXVALIDEP1 8 RW The rising edge of either USB_RXVALIDEP1y bit interrupt enable INT_USBRXVALIDEP0 7 RW The ris...

Page 165: ...channels for Input capture Output compare PWM generation edge and center aligned mode One pulse mode output Synchronization circuit to control the timer with external signals and to interconnect the timers Flexible clock source selection Peripheral clock PCLK at 6 or 12 MHz 32 768 kHz external clock if available 1 kHz clock GPIO input Interrupt generation on the following events Update counter ove...

Page 166: ...ts are interconnected 10 2 GPIO Usage The timers can optionally use GPIOs in the PA and PB ports for external inputs or outputs As with all EM358x digital inputs a GPIO used as a timer input can be shared with other uses of the same pin Available timer inputs include an external timer clock a clock mask and four input channels Any GPIO used as a timer output must be configured as an alternate outp...

Page 167: ...t up down or alternate up and down The counter clock can be divided by a prescaler The counter the auto reload register and the prescaler register can be written to or read by software This is true even when the counter is running The time base unit includes Counter Register TIMx_CNT Prescaler Register TIMx_PSC Auto Reload Register TIMx_ARR Some timer registers cannot be directly accessed by softw...

Page 168: ...n be generated at each counter overflow by setting the TIM_UG bit in the TIMx_EGR register or by using the slave mode controller Software can disable the UEV by setting the TIM_UDIS bit in the TIMx_CR1 register to avoid updating the shadow registers while writing new values in the buffer registers No UEV will occur until the TIM_UDIS bit is written to 0 Both the counter and the prescaler counter r...

Page 169: ...es of the counter behavior for different clock frequencies when TIMx_ARR 0x36 Figure 10 3 Counter Timing Diagram Internal Clock Divided by 1 Figure 10 4 Counter Timing Diagram Internal Clock Divided by 4 Figure 10 5 Counter Timing Diagram Update Event when TIM_ARBE 0 TIMx_ARR not buffered ...

Page 170: ...ounter restarts from 0 but the prescale rate doesn t change In addition if the TIM_URS bit in the TIMx_CR1 register is set setting the TIM_UG bit generates a UEV but without setting the INT_TIMUIF flag Thus no interrupt request is sent This avoids generating both update and capture interrupts when clearing the counter on the capture event When a UEV occurs the update flag the INT_TIMUIF bit in the...

Page 171: ...hadow registers while writing new values in the buffer registers Then no UEV occurs until the TIM_UDIS bit has been written to 0 However the counter continues counting up and down based on the current auto reload value In addition if the TIM_URS bit in the TIMx_CR1 register is set setting the TIM_UG bit generates a UEV but without setting the INT_TIMUIF flag Thus no interrupt request is sent This ...

Page 172: ...EM358x 172 Rev 0 4 Figure 10 9 Counter Timing Diagram Internal Clock Divided by 1 TIMx_ARR 0x6 Figure 10 10 Counter Timing Diagram Update Event with TIM_ARBE 1 counter underflow ...

Page 173: ...details 10 3 3 1 Internal Clock Source CK_INT The internal clock is selected when the slave mode controller is disabled TIM_SMS 000 in the TIMx_SMCR register In this mode the TIM_CEN TIM_DIR in the TIMx_CR1 register and TIM_UG bits in the TIMx_EGR register are actual control bits and can be changed only by software except for TIM_UG which remains cleared automatically As soon as the TIM_CEN bit is...

Page 174: ...Select rising edge polarity Write TIM_CC2P 0 in the TIMx_CCER register Configure the timer in external clock mode 1 Write TIM_SMS 111 in the TIMx_SMCR register Select TI2 as the input source Write TIM_TS 110 in the TIMx_SMCR register Enable the counter Write TIM_CEN 1 in the TIMx_CR1 register When a rising edge occurs on TI2 the counter counts once and the INT_TIMTIF flag is set The delay between ...

Page 175: ... Block For example to configure the up counter to count each 2 rising edges on ETR use the following procedure As no filter is needed in this example write TIM_ETF 0000 in the TIMx_SMCR register Set the prescaler Write TIM_ETPS 01 in the TIMx_SMCR register Select rising edge detection on ETR WriteTIM_ETP 0 in the TIMx_SMCR register Enable external clock mode 2 Write TIM_ECE 1 in the TIMx_SMCR regi...

Page 176: ...tered signal TIyF Then an edge detector with polarity selection generates a signal TIyFPy which can be used either as trigger input by the slave mode controller or as the capture command It is prescaled before the capture register ICyPS Figure 10 17 Capture Compare Channel Example Channel 1 Input Stage The output stage generates an intermediate reference signal OCyREF which is only used internally...

Page 177: ...er As soon as TIM_CC1S becomes different from 00 the channel is configured in input and the TIMx_CCR1 register becomes read only Program the required input filter duration with respect to the signal connected to the timer when the input is one of the TIy ICyF bits in the TIMx_CCMR1 register Consider a situation in which when toggling the input signal is unstable during at most 5 internal clock cyc...

Page 178: ...nput for TIMx_CCR1 write the TIM_CC1S bits to 01 in the TIMx_CCMR1 register TI1 selected Select the active polarity for TI1FP1 used both for capture in the TIMx_CCR1 and counter clear by writing the TIM_CC1P bit to 0 active on rising edge Select the active input for TIMx_CCR2by writing the TIM_CC2S bits to 10 in the TIMx_CCMR1 register TI1 selected Select the active polarity for TI1FP2 used for ca...

Page 179: ...CCMR1 register and the output polarity the TIM_CCyP bit in the TIMx_CCER register The output can be frozen TIM_OCyM 000 be set active TIM_OCyM 001 be set inactive TIM_OCyM 010 or can toggle TIM_OCyM 011 on the match Sets a flag in the interrupt flag register the INT_TIMCCyIF bit in the INT_TIMxFLAG register Generates an interrupt if the corresponding interrupt mask is set the TIM_CCyIF bit in the ...

Page 180: ... in the TIMx_EGR register OCy polarity is software programmable using the TIM_CCyP bit in the TIMx_CCER register It can be programmed as active high or active low OCy output is enabled by the TIM_CCyE bit in the TIMx_CCER register Refer to the TIMx_CCER register description in the Registers section for more details In PWM mode 1 or 2 TIMx_CNT and TIMx_CCRy are always compared to determine whether ...

Page 181: ...t 1 Zero percent PWM is not possible in this mode 10 3 9 3 PWM Center Aligned Mode Center aligned mode is active except when the TIM_CMS bits in the TIMx_CR1 register are 00 all configurations where TIM_CMS is non zero have the same effect on the OCyREF OCy signals The compare flag is set when the counter counts up when it counts down or when it counts up and down depending on the TIM_CMS bits con...

Page 182: ...ection is not updated when the value written to the counter that is greater than the auto reload value TIMx_CNT TIMx_ARR For example if the counter was counting up it continues to count up The direction is updated when 0 or the TIMx_ARR value is written to the counter but no UEV is generated The safest way to use center aligned mode is to generate an update by software setting the TIM_UG bit in th...

Page 183: ...IMx_SMCR register trigger mode The OPM waveform is defined Write the compare registers taking into account the clock frequency and the counter prescaler The tDELAY is defined by the value written in the TIMx_CCR1 register The tPULSE is defined by the difference between the auto reload value and the compare value TIMx_ARR TIMx_CCR1 To build a waveform with a transition from 0 to 1 when a compare ma...

Page 184: ...down and hardware modifies the TIM_DIR bit in the TIMx_CR1 register accordingly The TIM_DIR bit is calculated at each transition on any input TI1 or TI2 whether the counter is counting on TI1 only TI2 only or both TI1 and TI2 Encoder interface mode acts simply as an external clock with direction selection This means that the counter counts continuously between 0 and the auto reload value in the TI...

Page 185: ...s an example of counter behavior when IC1FP1 polarity is inverted same configuration as above except TIM_CC1P 1 Figure 10 26 Example of Encoder Interface Mode with IC1FP1 Polarity Inverted The timer configured in encoder interface mode provides information on a sensor s current position To obtain dynamic information speed acceleration deceleration measure the period between two encoder events usin...

Page 186: ..._CR1 register The counter starts counting on the internal clock then behaves normally until the TI1 rising edge When TI1 rises the counter is cleared and restarts from 0 In the meantime the trigger flag is set the INT_TIMTIF bit in the INT_TIMxFLAG register and an interrupt request can be sent if enabled depending on the INT_TIMTIF bit in the INT_TIMxCFG register Figure 10 27 shows this behavior w...

Page 187: ...input capture source only TIM_CC2S 01 in the TIMx_CCMR1 register Write TIM_CC2P 0 in the TIMx_CCER register to validate the polarity and detect high level only Configure the timer in trigger mode Write TIM_SMS 110 in the TIMx_SMCR register Select TI2 as the input source by writing TIM_TS 110 in the TIMx_SMCR register When a rising edge occurs on TI2 the counter starts counting on the internal cloc...

Page 188: ...n ETRP input Figure 10 30 Control circuit in External Clock Mode 2 Trigger Mode 10 3 15 Timer Synchronization The two timers can be linked together internally for timer synchronization or chaining A timer configured in master mode can reset start stop or clock the counter of the other timer configured in slave mode Figure 10 31 presents an overview of the trigger selection and the master mode sele...

Page 189: ...ck is not synchronized with counter 1 this mode only affects the Timer 2 counter enable signal Figure 10 32 Gating Timer 2 with OC1REF of Timer 1 In the example in Figure 10 32 the Timer 2 counter and prescaler are not initialized before being started So they start counting from their current value It is possible to start from a given value by resetting both timers before starting Timer 1 then wri...

Page 190: ...imer 2 is set with the UEV of Timer 1 Timer 2 starts counting from its current value which can be non zero on the divided internal clock as soon as Timer 1 generates the UEV When Timer 2 receives the trigger signal its TIM_CEN bit is automatically set and the counter counts until 0 is written to the TIM_CEN bit in the TIM2_CR1 register Both counter clock frequencies are divided by 3 by the prescal...

Page 191: ...nfigured in master slave mode slave with respect to TI1 master with respect to Timer 2 Configure Timer 1 in master mode to send its Enable as trigger output Write TIM_MMS 001 in the TIM1_CR2 register Configure Timer 1 slave mode to get the input trigger from TI1 Write TIM_TS 100 in the TIM1_SMCR register Configure Timer 1 in trigger mode Write TIM_SMS 110 in the TIM1_SMCR register Configure the Ti...

Page 192: ...ternal Input capture or clock TIy after filtering and edge detection ICyPS Internal Input capture signal after filtering edge detection and prescaling input to the capture register ITR0 Internal Internal trigger input connected to the other timer s output TRGO OCy External Output compare TIMxCy when used as an output Same as OCyREF but includes possible polarity inversion OCyREF Internal Output co...

Page 193: ...trigger either edge in gated mode INT_TIMCCRyIF set by a channel y input capture or output compare event INT_TIMUIF set by a UEV Clear bits in INT_TIMxFLAG by writing a 1 to their bit position When a channel is in capture mode reading the TIMx_CCRy register will also clear the INT_TIMCCRyIF bit The INT_TIMxCFG register controls whether or not the INT_TIMxFLAG bits actually request a top level NVIC...

Page 194: ...DIR 01 Center aligned mode 1 The counter counts up and down alternatively Output compare interrupt flags of configured output channels TIM_CCyS 00 in TIMx_CCMRy register are set only when the counter is counting down 10 Center aligned mode 2 The counter counts up and down alternatively Output compare interrupt flags of configured output channels TIM_CCyS 00 in TIMx_CCMRy register are set only when...

Page 195: ...w TIM_UDIS 1 RW Update Disable 0 A UEV is generated as soon as a counter overflow occurs a software update is generated or a hardware reset is generated by the slave mode controller Shadow registers are then loaded with their buffer register values 1 A UEV is not generated and shadow registers keep their value TIMx_ARR TIMx_PSC TIMx_CCRy The counter and the prescaler are reinitialized if the TIM_U...

Page 196: ...n reset mode then the signal on TRGO is delayed compared to the actual reset 001 Enable counter enable signal CNT_EN is trigger output This mode is used to start both timers at the same time or to control a window in which a slave timer is enabled The counter enable signal is generated by either the TIM_CEN control bit or the trigger input when configured in gated mode When the counter enable sign...

Page 197: ...rnal clock mode 2 disabled 1 External clock mode 2 enabled The counter is clocked by any active edge on the ETRF signal Note 1 Setting the TIM_ECE bit has the same effect as selecting external clock mode 1 with TRGI connected to ETRF TIM_SMS 111 and TIM_TS 111 Note 2 It is possible to use this mode simultaneously with the following slave modes reset mode gated mode and trigger mode TRGI must not b...

Page 198: ... PCLK 16 N 8 1101 Fsampling PCLK 32 N 5 1110 Fsampling PCLK 32 N 6 1111 Fsampling PCLK 32 N 8 Note PCLK is 12 MHz when the EM358x is using the 24 MHz crystal oscillator and 6 MHz if using the 12 MHz RC oscillator TIM_MSM 7 RW Master Slave Mode 0 No action 1 The effect of an event on the trigger input TRGI is delayed to allow exact synchronization between the current timer and the slave through TRG...

Page 199: ...he level of the other input 100 Reset Mode Rising edge of the selected trigger signal TRGI reinitializes the counter and generates an update of the registers 101 Gated Mode The counter clock is enabled when the trigger signal TRGI is high The counter stops but is not reset as soon as the trigger becomes low Both starting and stopping the counter are controlled 110 Trigger Mode The counter starts a...

Page 200: ...gured as input channel The TIM_CC4IF flag is set The INT_TIMMISSCC4IF flag is set if the TIM_CC4IF flag was already high The current value of the counter is captured in TMRx_CCR4 register TIM_CC3G 3 W Capture Compare 3 Generation 0 Does nothing 1 If CC3 configured as output channel The TIM_CC3IF flag is set If CC3 configured as input channel The TIM_CC3IF flag is set The INT_TIMMISSCC3IF flag is s...

Page 201: ... set if the TIM_CC1IF flag was already high The current value of the counter is captured in TMRx_CCR1 register TIM_UG 0 W Update Generation 0 Does nothing 1 Re initializes the counter and generates an update of the registers This also clears the prescaler counter but the prescaler ratio is not affected The counter is cleared if center aligned mode is selected or if TIM_DIR 0 up counting otherwise ...

Page 202: ...ence signal OC2REF from which OC2 derives OC2REF is active high whereas OC2 s active level depends on the TIM_CC2P bit 000 Frozen The comparison between the output compare register TIMx_CCR2 and the counter TIMx_CNT has no effect on the outputs 001 Set OC2REF to active on match The OC2REF signal is forced high when the counter TIMx_CNT matches the capture compare register 2 TIMx_CCR2 010 Set OC2RE...

Page 203: ...independently from the result of the comparison Delay to sample the trigger input and to activate OC2 output is reduced to 3 clock cycles TIM_OC2FE acts only if the channel is configured in PWM 1 or PWM 2 mode TIM_IC2F 15 12 RW Input Capture 1 Filter Applies only if TIM_CC2S 0 This defines the frequency used to sample the TI2 input Fsampling and the length of the digital filter applied to TI2 The ...

Page 204: ...pare 1 Buffer Enable Applies only if TIM_CC1S 0 See TIM_OC2BE description above TIM_OC1FE 2 RW Output Compare 1 Fast Enable Applies only if TIM_CC1S 0 See TIM_OC2FE description above TIM_IC1F 7 4 RW Input Capture 1 Filter Applies only if TIM_CC1S 0 See TIM_IC2F description above TIM_IC1PSC 3 2 RW Input Capture 1 Prescaler Applies only if TIM_CC1S 0 See TIM_IC2PSC description above TIM_CC1S 1 0 RW ...

Page 205: ...ence signal OC4REF from which OC4 derives OC4REF is active high whereas OC4 s active level depends on the TIM_CC4P bit 000 Frozen The comparison between the output compare register TIMx_CCR4 and the counter TIMx_CNT has no effect on the outputs 001 Set OC4REF to active on match The OC4REF signal is forced high when the counter TIMx_CNT matches the capture compare register 4 TIMx_CCR4 010 Set OC4RE...

Page 206: ...independently from the result of the comparison Delay to sample the trigger input and to activate OC4 output is reduced to 3 clock cycles TIM_OC4FE acts only if the channel is configured in PWM 1 or PWM 2 mode TIM_IC4F 15 12 RW Input Capture 4 Filter Applies only if TIM_CC4S 0 This defines the frequency used to sample the TI4 input Fsampling and the length of the digital filter applied to TI4 The ...

Page 207: ...pare 3 Buffer Enable Applies only if TIM_CC3S 0 See TIM_OC4BE description above TIM_OC3FE 2 RW Output Compare 3 Fast Enable Applies only if TIM_CC3S 0 See TIM_OC4FE description above TIM_IC3F 7 4 RW Input Capture 3 Filter Applies only if TIM_CC3S 0 See TIM_IC4F description above TIM_IC3PSC 3 2 RW Input Capture 3 Prescaler Applies only if TIM_CC3S 0 See TIM_IC4PSC description above TIM_CC3S 1 0 RW ...

Page 208: ...If CC4 configured as an input channel 0 IC4 is not inverted Capture occurs on a rising edge of IC4 When used as an external trigger IC4 is not inverted 1 IC4 is inverted Capture occurs on a falling edge of IC4 When used as an external trigger IC4 is inverted TIM_CC4E 12 RW Capture Compare 4 output Enable If CC4 is configured as an output channel 0 OC4 is disabled 1 OC4 is enabled If CC4 configured...

Page 209: ...F024 Reset 0x0 TIM2_CNT Timer 2 Counter Register Address 0x40010024 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TIM_CNT 7 6 5 4 3 2 1 0 TIM_CNT Bitname Bitfield Access Description TIM_CNT 15 0 RW Counter value ...

Page 210: ...7 6 5 4 3 2 1 0 0 0 0 0 TIM_PSC Bitname Bitfield Access Description TIM_PSC 3 0 RW The prescaler divides the internal timer clock frequency The counter clock frequency CK_CNT is equal to fCK_PSC 2 TIM_PSC Clock division factors can range from 1 through 32768 The division factor is loaded into the shadow prescaler register at each UEV including when the counter is cleared through TIM_UG bit of TMR1...

Page 211: ...be loaded in the shadow auto reload register The auto reload register is buffered Writing or reading the auto reload register accesses the buffer register The content of the buffer register is transfered in the shadow register permanently or at each UEV depending on the auto reload buffer enable bit TIM_ARBE in TMRx_CR1 register The UEV is sent when the counter reaches the overflow point or underf...

Page 212: ... is configured as an output TIM_CC1S 0 TIM_CCR1 is the buffer value to be loaded in the actual capture compare 1 register It is loaded permanently if the preload feature is not selected in the TMR1_CCMR1 register bit OC1PE Otherwise the buffer value is copied to the shadow capture compare 1 register when an UEV occurs The active capture compare register contains the value to be compared to the cou...

Page 213: ...0 TIM2_CCR2 Timer 2 Capture Compare Register 2 Address 0x40010038 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TIM_CCR 7 6 5 4 3 2 1 0 TIM_CCR Bitname Bitfield Access Description TIM_CCR 15 0 RW See description in the TIMx_CCR1 register ...

Page 214: ...0 TIM2_CCR3 Timer 2 Capture Compare Register 3 Address 0x4001003C Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TIM_CCR 7 6 5 4 3 2 1 0 TIM_CCR Bitname Bitfield Access Description TIM_CCR 15 0 RW See description in the TIMx_CCR1 register ...

Page 215: ...0 TIM2_CCR4 Timer 2 Capture Compare Register 4 Address 0x40010040 Reset 0x0 31 30 29 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 TIM_CCR 7 6 5 4 3 2 1 0 TIM_CCR Bitname Bitfield Access Description TIM_CCR 15 0 RW See description in the TIMx_CCR1 register ...

Page 216: ...VD TIM_CLKMSKEN TIM_EXTRIGSEL Bitname Bitfield Access Description TIM_ORRSVD 3 RW Reserved this bit must always be set to 0 TIM_CLKMSKEN 2 RW Enables TIM1MSK when TIM1CLK is selected as the external trigger 0 TIM1MSK not used 1 TIM1CLK is ANDed with the TIM1MSK input TIM_EXTRIGSEL 1 0 RW Selects the external trigger used in external clock mode 2 0 PCLK 1 calibrated 1 kHz clock 2 32 kHz reference c...

Page 217: ... for TIM2C4 0 PA2 1 PB4 TIM_REMAPC3 6 RW Selects the GPIO used for TIM2C3 0 PA1 1 PB3 TIM_REMAPC2 5 RW Selects the GPIO used for TIM2C2 0 PA3 1 PB2 TIM_REMAPC1 4 RW Selects the GPIO used for TIM2C1 0 PA0 1 PB1 TIM_ORRSVD 3 RW Reserved this bit must always be set to 0 TIM_CLKMSKEN 2 RW Enables TIM2MSK when TIM2CLK is selected as the external trigger 0 TIM2MSK not used 1 TIM2CLK is ANDed with the TI...

Page 218: ...0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 INT_TIMTIF 0 INT_TIMCC4IF INT_TIMCC3IF INT_TIMCC2IF INT_TIMCC1IF INT_TIMUIF Bitname Bitfield Access Description INT_TIMTIF 6 RW Trigger interrupt enable INT_TIMCC4IF 4 RW Capture or compare 4 interrupt enable INT_TIMCC3IF 3 RW Capture or compare 3 interrupt enable INT_TIMCC2IF 2 RW Capture or compare 2 interrupt enable INT_TIMCC1IF 1 RW Cap...

Page 219: ...IMRSVD 0 7 6 5 4 3 2 1 0 0 INT_TIMTIF 0 INT_TIMCC4IF INT_TIMCC3IF INT_TIMCC2IF INT_TIMCC1IF INT_TIMUIF Bitname Bitfield Access Description INT_TIMRSVD 12 9 R May change during normal operation INT_TIMTIF 6 RW Trigger interrupt INT_TIMCC4IF 4 RW Capture or compare 4 interrupt pending INT_TIMCC3IF 3 RW Capture or compare 3 interrupt pending INT_TIMCC2IF 2 RW Capture or compare 2 interrupt pending IN...

Page 220: ...15 14 13 12 11 10 9 8 0 0 0 INT_TIMMISSCC4IF INT_TIMMISSCC3IF INT_TIMMISSCC2IF INT_TIMMISSCC1IF 0 7 6 5 4 3 2 1 0 0 INT_TIMMISSRSVD Bitname Bitfield Access Description INT_TIMMISSCC4IF 12 RW Capture or compare 4 interrupt missed INT_TIMMISSCC3IF 11 RW Capture or compare 3 interrupt missed INT_TIMMISSCC2IF 10 RW Capture or compare 2 interrupt missed INT_TIMMISSCC1IF 9 RW Capture or compare 1 interr...

Page 221: ...tial inputs the ADC input stage always operates in differential mode Single ended conversions are performed by connecting one of the differential inputs to VREF 2 while fully differential operation uses two external inputs Note The regulator input voltage VDD_PADS cannot be measured using the ADC but it can be measured through Ember software 11 1 Setup and Configuration To use the ADC follow this ...

Page 222: ...on for more information on using an external reference 11 1 3 Offset Gain Correction When a conversion is complete the 16 bit converted data is processed in several steps by offset gain correction hardware 1 The initial signed ADC conversion result is added to the 16 bit signed two s complement value of the ADC offset register ADC_OFFSET 2 The offset corrected data is multiplied by the 16 bit ADC ...

Page 223: ...DMA is reset When the DMA fills the lower and upper halves of the buffer it sets the INT_ADCULDHALF and INT_ADCULDFULL bits respectively in the INT_ADCFLAG register The current location to which the DMA is writing can also be determined by reading the ADC_DMACUR register 11 1 5 ADC Configuration Register The ADC configuration register ADC_CFG sets up most of the ADC operating parameters 11 1 5 1 I...

Page 224: ...differential input range is fixed as VREF to VREF 11 1 5 3 Sample Time ADC sample time is programmed by selecting the sampling clock and the clocks per sample The sampling clock may be either 1 MHz or 6 MHz If the ADC_1MHZCLK bit in the ADC_CFG register is clear the 6 MHz clock is used if it is set the 1 MHz clock is selected The 6 MHz sample clock offers faster conversion times but the ADC resolu...

Page 225: ...in correction multiplication exceeded the limits for a signed 16 bit number gain saturation INT_ADCULDFULL the DMA wrote to the last location in the buffer DMA buffer full INT_ADCULDHALF the DMA wrote to the last location of the first half of the DMA buffer DMA buffer half full INT_ADCDATA there is data ready in the ADC_DATA register Bits in INT_ADCFLAG register may be cleared by writing a 1 to th...

Page 226: ...DATA register The following procedure illustrates a simple polled method of using the ADC with DMA After completing the procedure the latest conversion results are available in the location written to by the DMA This assumes that any GPIOs and the voltage reference have already been configured 1 Allocate a 16 bit signed variable for example analogData to receive the ADC output Make sure that analo...

Page 227: ...ot yield the minimum 16 bit two s complement value 32768 as the conversion result Instead VGND yields a value close to 57344 when the input buffer is not selected VGND cannot be measured when the input buffer is enabled because it is outside the buffer s input range NVREF is a sampling of VREF Due to the ADC s internal design VREF does not yield the maximum positive 16 bit two s complement 32767 a...

Page 228: ...ed Differential 5 6 5 6 7 1 7 1 8 6 8 6 10 0 10 1 11 3 11 4 12 2 12 5 12 4 12 9 12 5 12 9 ENOB from SINAD Single Ended Differential 5 5 5 6 7 0 7 0 8 5 8 5 9 9 10 0 10 9 11 3 11 2 12 1 11 3 12 3 11 3 12 4 Equivalent ADC Bits 7 15 9 8 15 8 9 15 7 10 15 6 11 15 5 12 15 4 13 15 3 14 15 2 Note INL and DNL are referenced to a LSB of the Equivalent ADC Bits shown in the last row of Table 11 6 ENOB effec...

Page 229: ...68 70 71 75 71 77 71 77 SDFR dB Single Ended Differential 60 60 68 69 75 77 75 80 75 80 75 80 75 80 75 80 THD dB Single Ended Differential 45 45 54 54 63 63 68 71 70 76 70 77 70 78 70 78 ENOB from SNR Single Ended Differential 5 6 5 6 7 1 7 1 8 6 8 6 10 0 10 1 11 4 11 5 12 1 12 5 12 4 12 9 12 5 13 0 ENOB from SINAD Single Ended Differential 5 5 5 6 7 0 7 1 8 5 8 6 9 9 10 1 11 0 11 4 11 4 12 4 11 5...

Page 230: ...8 0 017 0 02 0 04 0 077 0 167 0 326 0 65 DNL codes RMS 0 01 0 006 0 006 0 007 0 008 0 013 0 023 0 038 ENOB from single cycle test 3 6 5 0 6 6 8 1 9 5 10 7 11 3 11 6 SNR dB Single Ended Differential 23 23 32 32 41 41 50 50 59 59 65 66 67 69 68 71 SINAD dB Single Ended Differential 23 23 32 32 41 41 50 50 58 59 64 66 66 69 66 71 SDFR dB Single Ended Differential 48 48 56 57 65 65 72 74 72 82 72 88 7...

Page 231: ...nimum input voltage 0 V Maximum input voltage VREF V Single ended signal range 0 VREF V Differential signal range VREF VREF V Common mode range 0 VREF V Input referred ADC offset 10 10 mV Input Impedance 1 MHz sample clock 6 MHz sample clock Not sampling 1 0 5 10 MΩ Note The signal ended ADC measurements are limited in their range and only guaranteed for accuracy within the limits shown in this ta...

Page 232: ...0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ADC_DATA_FIELD 7 6 5 4 3 2 1 0 ADC_DATA_FIELD Bitname Bitfield Access Description ADC_DATA_FIELD 15 0 R ADC conversion result The result is a signed 2 s complement value The significant bits of the value begin at bit 15 regardless of the sample period used ...

Page 233: ...RW Reserved these bits must be set to 0 ADC_MUXP 10 7 RW Input selection for the P channel 0x0 PB5 pin 0x1 PB6 pin 0x2 PB7 pin 0x3 PC1 pin 0x4 PA4 pin 0x5 PA5 pin 0x8 GND 0V not for high voltage range 0x9 VREF 2 0 6V 0xA VREF 1 2V 0xB VDD_PADSA 2 0 9V not for high voltage range 0x6 0x7 0xC 0xF reserved ADC_MUXN 6 3 RW Input selection for the N channel Refer to ADC_MUXP above for choices ADC_1MHZCL...

Page 234: ...27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ADC_OFFSET_FIELD 7 6 5 4 3 2 1 0 ADC_OFFSET_FIELD Bitname Bitfield Access Description ADC_OFFSET_FIELD 15 0 RW 16 bit signed offset added to the basic ADC conversion result before gain correction is applied ...

Page 235: ...ADC_GAIN_FIELD 7 6 5 4 3 2 1 0 ADC_GAIN_FIELD Bitname Bitfield Access Description ADC_GAIN_FIELD 15 0 RW Gain factor that is multiplied by the offset corrected ADC result to produce the output value The gain is a 16 bit unsigned scaled integer value with a binary decimal point between bits 15 and 14 It can represent values from 0 to almost 2 The reset value is a gain factor of 1 ...

Page 236: ...ADC_DMARST 0 0 ADC_DMAAUTOWRAP ADC_DMALOAD Bitname Bitfield Access Description ADC_DMARST 4 W Write 1 to reset the ADC DMA This bit auto clears ADC_DMAAUTOWRAP 1 RW Selects DMA mode 0 Linear mode the DMA stops when the buffer is full 1 Auto wrap mode the DMA output wraps back to the start when the buffer is full ADC_DMALOAD 0 RW Loads the DMA buffer Write 1 to start DMA writing 0 has no effect Cle...

Page 237: ... 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 0 0 0 0 0 0 0 7 6 5 4 3 2 1 0 0 0 0 0 0 0 ADC_DMAOVF ADC_DMAACT Bitname Bitfield Access Description ADC_DMAOVF 1 R DMA overflow occurs when an ADC result is ready and the DMA is not active Cleared by DMA reset ADC_DMAACT 0 R DMA status reads 1 if DMA is active ...

Page 238: ...26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ADC_DMABEG 7 6 5 4 3 2 1 0 ADC_DMABEG Bitname Bitfield Access Description ADC_DMABEG 15 0 RW ADC buffer start address Caution this must be an even address the least significant bit of this register is fixed at zero by hardware ...

Page 239: ... 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 ADC_DMASIZE_FIELD 7 6 5 4 3 2 1 0 ADC_DMASIZE_FIELD Bitname Bitfield Access Description ADC_DMASIZE_FIELD 14 0 RW ADC buffer size This is the number of 16 bit ADC conversion results the buffer can hold not its length in bytes The length in bytes is twice this value ...

Page 240: ...20000000 31 30 29 28 27 26 25 24 0 0 1 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 ADC_DMACUR_FIELD 7 6 5 4 3 2 1 0 ADC_DMACUR_FIELD 0 Bitname Bitfield Access Description ADC_DMACUR_FIELD 15 1 R Current DMA address the location that will be written next by the DMA ...

Page 241: ... 28 27 26 25 24 0 0 0 0 0 0 0 0 23 22 21 20 19 18 17 16 0 0 0 0 0 0 0 0 15 14 13 12 11 10 9 8 0 ADC_DMACNT_FIELD 7 6 5 4 3 2 1 0 ADC_DMACNT_FIELD Bitname Bitfield Access Description ADC_DMACNT_FIELD 14 0 R DMA count the number of 16 bit conversion results that have been written to the buffer ...

Page 242: ...5 4 3 2 1 0 0 0 0 INT_ADCOVF INT_ADCSAT INT_ADCULDFULL INT_ADCULDHALF INT_ADCFLAGRSVD Bitname Bitfield Access Description INT_ADCOVF 4 RW DMA buffer overflow interrupt pending INT_ADCSAT 3 RW Gain correction saturation interrupt pending INT_ADCULDFULL 2 RW DMA buffer full interrupt pending INT_ADCULDHALF 1 RW DMA buffer half full interrupt pending INT_ADCDATA 0 RW ADC_DATA register has data interr...

Page 243: ... 0 7 6 5 4 3 2 1 0 0 0 0 INT_ADCOVF INT_ADCSAT INT_ADCULDFULL INT_ADCULDHALF INT_ADCCFGRSVD Bitname Bitfield Access Description INT_ADCOVF 4 RW DMA buffer overflow interrupt enable INT_ADCSAT 3 RW Gain correction saturation interrupt enable INT_ADCULDFULL 2 RW DMA buffer full interrupt enable INT_ADCULDHALF 1 RW DMA buffer half full interrupt enable INT_ADCDATA 0 RW ADC_DATA register has data inte...

Page 244: ...D signals into the data packet stream so that trace data can be re associated with its trace source Trace Out The trace out block serializes the data and sends it off chip by the proper alternate output GPIO functions The five pins available to the TPIU are SWO TRACECLK TRACEDATA0 TRACEDATA1 TRACEDATA2 TRACEDATA3 Since these pins are alternate outputs of GPIO refer to Chapter 7 GPIO and in the Emb...

Page 245: ...ate packets at the same time the ITM arbitrates the order in which the packets are output The three sources in decreasing order of priority are Software trace Software can write directly to ITM stimulus registers emitting packets Hardware trace The DWT generates packets that the ITM emits Time stamping Timestamps are emitted relative to packets and the ITM contains a 21 bit counter to generate the...

Page 246: ...pture only select trace information and only after a specific sequence of conditions When the system is running the ETM collects instruction data compresses this information and delivers it off chip in real time for post processing The ETM emits trace information to the Trace Port Interface Unit TPIU The TPIU combines the other sources of debug data DWT and ITM and outputs it to the trace pins For...

Page 247: ... combined with software events and timestamp packets for transmission through the ITM TPIU A core halt entry to debug state When exception tracing is enabled the DWT emits an exception trace packet under the following conditions Exception entry from thread mode or pre emption of a thread or handler Exception exit when exiting a handler Exception return when re entering a pre empted thread or handl...

Page 248: ...apped to the address defined in the remap register plus and offset corresponding to the comparator that matched Alternately the address is remapped to a breakpoint instruction The comparison happens on the fly but the result of the comparison occurs too late to stop the original instruction fetch or literal load taking place from the flash space The processor ignores this transaction however and o...

Page 249: ...ction and protection from glitches The ARM CoreSight TM Debug Access Port DAP comprises the Serial Wire and JTAG Interface SWJ As illustrated in Figure 17 1 the DAP includes two primary components a debug port the SWJ DP and an access port the AHB AP The SWJ DP provides external debug access while the AHB AP provides internal bus access An external debug tool connected to the EM358x s debug pins c...

Page 250: ...r 1 Missed Interrupt Register 4000A81C INT_TIM2MISS RW 0 Timer 2 Missed Interrupts Register 4000A820 INT_MISS RW 0 Top Level Missed Interrupts Register 4000A840 INT_TIM1CFG RW 0 Timer 1 Interrupt Configuration Register 4000A844 INT_TIM2CFG RW 0 Timer 2 Interrupt Configuration Register 4000A848 INT_SC1CFG RW 0 Serial Controller 1 Interrupt Configuration Register 4000A84C INT_SC2CFG RW 0 Serial Cont...

Page 251: ...O_PBSET RW 0 Port B Output Set Register 4000B214 GPIO_PBCLR RW 0 Port B Output Clear Register 4000B400 GPIO_PCCFGL RW 4444 Port C Configuration Register Low 4000B404 GPIO_PCCFGH RW 4444 Port C Configuration Register High 4000B408 GPIO_PCIN RW 0 Port C Input Data Register 4000B40C GPIO_PCOUT RW 0 Port C Output Data Register 4000B410 GPIO_PCSET RW 0 Port C Output Set Register 4000B414 GPIO_PCCLR RW ...

Page 252: ... R 0 TWI Status Register 4000C04C SC2_TWICTRL1 RW 0 TWI Control Register 1 4000C050 SC2_TWICTRL2 RW 0 TWI Control Register 2 4000C054 SC2_MODE RW 0 Serial Mode Register 4000C058 SC2_SPICFG RW 0 SPI Configuration Register 4000C060 SC2_RATELIN RW 0 Serial Clock Linear Prescaler Register 4000C064 SC2_RATEEXP RW 0 Serial Clock Exponential Prescaler Register 4000C070 SC2_RXCNTSAVED R 0 Saved Receive DM...

Page 253: ...Clock Exponential Prescaler Register 4000C868 SC1_UARTPER RW 0 UART Baud Rate Period Register 4000C86C SC1_UARTFRAC RW 0 UART Baud Rate Fractional Period Register 4000C870 SC1_RXCNTSAVED R 0 Saved Receive DMA Count Register BLOCK ADC 4000D000 4000DFFF Analog to Digital Converter Address Name Type Reset Description 4000E000 ADC_DATA R 0 ADC Data Register 4000E004 ADC_CFG RW 00001800 ADC Configurati...

Page 254: ...ter 3 4000F040 TIM1_CCR4 RW 0 Timer 1 Capture Compare Register 4 4000F050 TIM1_OR RW 0 Timer 1 Option Register BLOCK TIM2 4000F000 4000FFFF General Purpose Timer 2 Address Name Type Reset Description 40010000 TIM2_CR1 RW 0 Timer 2 Control Register 1 40010004 TIM2_CR2 RW 0 Timer 2 Control Register 2 40010008 TIM2_SMCR RW 0 Timer 2 Slave Mode Control Register 40010014 TIM2_EGR RW 0 Timer 2 Event Gen...

Page 255: ...Interrupts Configuration Register E000E180 INT_CFGCLR RW 0 Top Level Clear Interrupts Configuration Register E000E200 INT_PENDSET RW 0 Top Level Set Interrupts Pending Register E000E280 INT_PENDCLR RW 0 Top Level Clear Interrupts Pending Register E000E300 INT_ACTIVE R 0 Top Level Active Interrupts Register E000ED3C SCS_AFSR RW 0 Auxiliary Fault Status Register ...

Page 256: ... ADC and Interrupt registers Removed references to serial controllers 3 and 4 and made associated changes to serial controller text Revision 0 2 to Revision 0 3 Introduced EM358x and the 5 variants EM3581 EM3582 EM3585 EM3586 and EM3588 Revision 0 3 to Revision 0 4 Addition of EM3587 variant Correction of some references to EM358 ...

Page 257: ...boratories makes no warranty representation or guarantee regarding the suitability of its products for any particular purpose nor does Silicon Laboratories assume any liability arising out of the application or use of any product or circuit and specifically disclaims any and all liability including without limitation consequential or incidental damages Silicon Laboratories products are not designe...

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