KS8910 100/10 Mbps ETHERNET TRANSCEIVER
10BASE-T DIGITAL BLOCKS
5-5
Preliminary Spec. ver
1.4
LOOP-BACK FUNCTION
The 10BASE-T Transceiver provides the normal loopback function specified by the 10BASE-T standard for the
twisted-pair port. The loopback function operates in conjunction with the transmit function. Data transmitted by the
back-end is internally looped back within the 10BASE-T Transceiver from the TXD pin through the Manchester
encoder/decoder to the RXD pin and returned to the back-end. The normal loopback function is disabled when a
data collision occurs, clearing the RXD circuit for the TPI data. Normal loopback is also disabled during link fail and
jabber states.
The 10BASE-T Transceiver also provides three additional loopback functions. An external loopback mode, useful
for system-level testing, is controlled by LEDC. When LEDC is tied low, the 10BASE-T Transceiver disables the
collision detection and internal loopback circuits, to allow external loopback or full duplex operation. The 10BASE-T
Transceiver provides additional forced loopback functions controlled by LBK BMCR Register Bit. When the TP port
is selected and LBK=1, TP loopback is forced, overriding collisions on the TP circuit. When LBK=0, normal loop-
back is in effect.
LINK INTEGRITY TEST
Figure 5-4 is a state diagram of the 10BASE-T Transceiver Link Integrity test function. The link integrity test is used
to determine the status of the receive side twisted-pair cable. Link integrity testing is enabled when the LI pin is tied
high. When enabled, the receiver recognizes link integrity pulses which are transmitted in the absence of receive
traffic. If no serial data stream or link integrity pulses are detected within 50-150 ms, the chip enters a link fail state
and disables the transmit and normal loopback functions. The 10BASE-T Transceiver ignores any link integrity
pulse with an interval less than 2~7 ms. The 10BASE-T Transceiver will remain in the link fail state until it detects
either a serial data packet or two or more link integrity pulses.
Figure 5-4. State Diagram of Link Integrity Test Function
lit_dis-XMIT,
DO_active
lipd_link_test_rcv
RD_active
lnk_st_B10[1:0]
lit_dis_RCV,
lit_dis_LPBK
10Base-T
Link Status
Monitoring &
Control
link test min timer
link test max timer
link loss timer
Summary of Contents for KS8910
Page 1: ...20 8910 0599 USER S MANUAL KS8910 100 10 Mbps Ethernet Transceriver PHY Preliminary ...
Page 4: ...PRELIMINARY SPECIFICATION vi KS8910 100 10 Mbps ETHERNET CONTROLLER ...
Page 21: ...EXTERNAL SIGNALS KS8910 100 10 Mbps ETHERNET TRANSCEIVER 2 8 Preliminary Spec ver 1 4 MEMO ...
Page 89: ...APPLICATION NOTE KS8910 100 10 Mbps ETHERNET TRANSCEIVER 9 2 Preliminary Spec ver 1 4 MEMO ...
Page 91: ...MECHANICAL DATA KS8910 100 10 Mbps ETHERNET TRANSCEIVER 10 2 Preliminary Spec ver 1 4 MEMO ...
Page 99: ...A 8 APPENDIX KS8910 100 10 Mbps ETHERNET TRANSCEIVER Preliminary Spec ver 1 4 NOTES ...