KS8910 100/10 Mbps ETHERNET TRANSCEIVER
EXTERNAL SIGNALS
2-5
Preliminary Spec. ver
1.4
Signal
Pin Number
I/O
Description
Rx_clk
50
O
5T
t/s
Receive clock :
Rx_clk is a continuous clock. In 4-bit mode, its frequency is 25 MHz for
100Mbit/s operation, and 2.5 MHz for 10Mbit/s. RXD[3:0], Rx_DV, and
Rx_er are driven by the Transceiver off the falling edge of Rx_clk, and
sampled on the rising edge of Rx_clk.
RxD[3:0]
46,45,44,43
O
5T
t/s
Receive data
:
RxD is aligned on nibble boundaries. RxD[0] corresponds to the first bit
received on the physical medium which is the LSB of the byte in one clock
period and the fifth bit of that byte in the next clock.
Rx_DV
49
O
5T
t/s
Receive data valid :
PHY asserts Rx_DV synchronously and holds it active during the clock
periods that RxD[3:0] contains valid received data. The Transceiver
asserts Rx_DV no later than the clock period when it places the first
nibble of the start frame delimiter (SFD) on RxD[3:0]. If the Transceiver
asserts Rx_DV prior to the first nibble of the SFD, then RxD[3:0] carries
valid preamble symbols.
Rx_er
51
O
5T
t/s
Receive error :
PHY asserts Rx_er synchronously whenever it detects a physical medium
error, e.g., a coding violation. The Transceiver asserts Rx_er only when it
asserts Rx_DV.
MII Station Management Signals
The next sub-table shows the two MII station management signals. Use of these signals for configuring the
transceiver or negotiating a link protocol is optional.
MDC
42
I
5T
PD
Management Data Clock :
The timing reference for transfer of information on the MDIO signal. With
the PCI clock at 33 MHz, the MDC clock has a maximum clock frequency
of 33/14 = 2.36 MHz. The minimum clock period is 424 ns.
MDIO
41
I/O
5T
t/s
PD
Management Data I/O :
MDIO transfers control and status management data from the attached
MAC. MDIO Transmits status information from the PHY to the MAC.
LED INTERFACE
These signals allow connection of LEDs to monitor the status of the Transceiver. The next sub-table shows a
summary of the LED signals generated by the Transceiver.
LEDC[D4]
3
I/O
5T
t/s
Collision Indicator /Device ID4:
Pulled low for 10 ms when a collision is detected. Otherwise LEDC is high
LEDL[D3]
4
Link Integrity Indicator /Device ID3:
Pulled low during link test pass
LEDT[D2]
5
Transmit Indicator /Device ID2:
Table 2-1. KS8910 Signal Descriptions
Summary of Contents for KS8910
Page 1: ...20 8910 0599 USER S MANUAL KS8910 100 10 Mbps Ethernet Transceriver PHY Preliminary ...
Page 4: ...PRELIMINARY SPECIFICATION vi KS8910 100 10 Mbps ETHERNET CONTROLLER ...
Page 21: ...EXTERNAL SIGNALS KS8910 100 10 Mbps ETHERNET TRANSCEIVER 2 8 Preliminary Spec ver 1 4 MEMO ...
Page 89: ...APPLICATION NOTE KS8910 100 10 Mbps ETHERNET TRANSCEIVER 9 2 Preliminary Spec ver 1 4 MEMO ...
Page 91: ...MECHANICAL DATA KS8910 100 10 Mbps ETHERNET TRANSCEIVER 10 2 Preliminary Spec ver 1 4 MEMO ...
Page 99: ...A 8 APPENDIX KS8910 100 10 Mbps ETHERNET TRANSCEIVER Preliminary Spec ver 1 4 NOTES ...