Samsung KS8910, User Manual

Page: 33 / 99

100BASE-TX DIGITAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER
4-6
Preliminary Spec. ver
1.4
4B/5B ENCODER (TRANSMIT STM)
The 4B/5B Encoder converts the received data nibbles into 5-bit code groups. This is a trivial translation process
except for the first two nibbles of the preamble which are substituted by the Start-of-Stream Delimiter, SSD.
Likewise, an End-of-Stream Delimiter, ESD, is added to the end of the transmitted data packet. The data packet is
fully recovered by the receiving 5B/4B decoder, i.e. the ESD is stripped and the SSD is changed back to the
preamble bit pattern.
The collision signal, COL, is put into the active state when transmission and reception are detected at the same
time. The 4B/5B Encoder is implemented as a state machine. The state diagram is given in Figure 4-3. The state
“ERROR CHECK” of the state machine given in Figure 24-8 in the IEEE 802.3u standard has been merged into the
states “TRANSMIT” and “END STREAM T” for better efficiency.
4B/5B DECODER(RECEIVE STM)
The 5B/4B Decoder converts the received 5-bit code-groups into nibbles. In general, this is a trivial translation
process. However, preamble bits have to be substituted for the first two code-groups of a packet, the Start-of-
Frame Delimiter. The 5B/4B Decoder scans the incoming bit stream for the SSD and locks to it. After locking to the
incoming bit stream each 5-bit code group is translated into a nibble according to table 24-1 in the IEEE 802.3u
standard. The last two code-groups of a packet, which is the End-of-Stream Delimiter, are removed from the code
stream.
The states “CARRIER DETECT,” “CONFIRM K,” “START OF STREAM J” and “START OF STREAM K” in figure
24-11 in the IEEE 802.3u standard have been combined into “CONFIRM J” and “CONFIRM K” for better efficiency.
The same is true for “RECEIVE,” “DATA,” “DATA ERROR,” “PREMATURE END” and “END OF STREAM” which
have been merged into the “DECODE” state.
In the “DECODE” and “START STREAM” states, the outputs’ values depend on the received bit stream. The
relationship appears in Table 4-2.
The 5B/4B decoder is implemented as a state machine with the state diagram shown in Figure 4-4.
Table 4-2. 5B/4B Outputs
OUTPUT 0 1
Rx_DV {esd1, esd2} else
Rx_er valid data / {esd1, esd2} else
init_RXbits else {esd1, esd2}