Samsung KS8910, User Manual

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FUNCTIONAL BLOCKS KS8910 100/10 Mbps ETHERNET TRANSCEIVER
3-6
Preliminary Spec. ver
1.4
Transmit Clock (TXPLL)
Internal clock synthesizer serves as internal master clock distribution system supplying all transmit clock reference.
The transmit clock block includes crystal oscillator, PLL frequency synthesis, and frequency divider functions
needed to generate all of the transmit clocks used in the design from a 25 MHz crystal attached to the chip. This
block generates 2.5 MHz, 10 MHz, 20 MHz, 25 MHz and 125 MHz clocks. The transmit frequency synthesizer
circuit uses an on-chip VCO.
Encoder (MLT-3)
The NRZI to MLT-3 Encoder receives the scrambled NRZI data stream from the PMA and encodes it into MLT-3 for
presentation to the Twisted-Pair Transmit Driver. MLT-3 coding has certain similtarities to NRZI, but three levels are
output instead of two, i.e. Positive voltage, Zero voltage and Negative voltage. A MLT-3 coded data stream keeps
cycling from Positive voltage to Zero voltage to Negative voltage and back to Positive voltage through Zero Voltage.
Each time a logic “1” is encoded a transition will take place. Each time a logic “0” is encoded the previous output
level will be maintained for another bit period.
Receive and Baseline Wander Equalization (RX EQ/BW EQ)
The receive equalizer compensates for amplitude and phase variations introduced by twisted pair cable. The
equalizer compensates the transfer functions of cables over the range of 0 meters to 100 meters.The equalization
circuit also corrects for baseline wander that is introduced by AC coupling transformers. The equalization circuits
require no off-chip components or external adjustments.
Signal Dectector
The Signal Detector monitors signal amplitude on cable and inform Digital Block about existence of 100
Rx_code_bit by checking link_status. Threshold of Detect Assertion is 400mVp-p and Detect Deassertion is
300mVp-p.
Receive Timing Recovery
The receive timing recovery circuit generates a 125 MHz clock and re-timed data from the equalized signal. The
timing recovery circuit uses an on-chip VCO.
Receive Squelch (RX SQ)
Receive squelch circuitry serves as receive signal slicer and noise rejector. The receive squelch circuit is activated
if the input signal amplitude is decreased below the carrier detect deassertion threshold of 300 mV peak-to-peak.
This prevents the transmission of high bit error rate data to the digital and protocol sections of the chip.
LED DRIVER
The KS8910 supports five status LEDs and LED pins are shared with PHY address.These pins can be externally
strapped as ‘High’ or ‘Low’ to encode different PHY addresses. When the pin is strapped to Low, the associated
LED will be actived to ‘High’. When the pin is strapped to ‘High’,the associated LED will be actived to ‘Low’