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KS8910 100/10 Mbps ETHERNET TRANSCEIVER

10BASE-T DIGITAL BLOCKS

5-3

Preliminary Spec. ver

1.4

SQE FUNCTION

The 10BASE-T transceiver supports the signal quality error (SQE) function as shown in Figure 5-3. If SQE register
is enabled after every successful transmission on the 10BASE-T network, the 10BASE-T transceiver transmits the
SQE signal to the DTE for ten 5 bit times over the internal CI Circuit.

If SQE is disabled, the 10Base-T transceiver does not transmit SQE signal.The default value of SQE register is dis-
able.

RECEIVE FUNCTION

The 10BASE-T transceiver receive function acquires timing and data from the twisted-pair network (the TPI cir-
cuit)). Valid received signals are passed through the on-chip filters and Manchester decoder and output as decoded
NRZ data and receive timing on the RXD and RCLK pins, respectively. No external filters are required. An internal
intelligent squelch function discriminates noise from link test pulses and valid data streams. The receive function is
activated only by valid data streams above the squelch level and with proper timing. If the differential signal at the
TPI circuit inputs falls below 75% of the threshold level (unsquelched) for eight bit times (typical), the 10BASE-T
transceiver receive function enters the idle state. If the polarity of the TPI circuit is reversed, the 10BASE-T trans-
ceiver detects the polarity reversal and reports it via the PLR output. The 10BASE-T transceiver automatically cor-
rects reversed polarity.

POLARITY REVERSE FUNCTION

The 10BASE-T transceiver polarity reverse function uses both link pulses and end-of-frame data to determine the
polarity of the received signal. A reversed polarity condition is detected when eight opposite receive link pulses are
detected without receipt of a link pulse of the expected polarity. Reversed polarity is also detected if four frames are
received with a reversed start-of-idle. Whenever polarity is reversed, these two counters are reset to zero. If the
10BASE-T transceiver enters the link fail state and no valid data or link pulses are received within 96 to 128 ms the
polarity is reset to the default non-flipped condition. If Link Integrity Testing is disabled, polarity detection is based
only on received data. The polarity reverse function can be controlled by B10CR register.

Figure 5-2. SQE Function

sqet_ci_sqe

XMIT_EN

DO_active

CLK(20MHz)

wait 1us after

transmit finished

Generation sqet

signal 1us

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Summary of Contents for KS8910

Page 1: ...20 8910 0599 USER S MANUAL KS8910 100 10 Mbps Ethernet Transceriver PHY Preliminary ...

Page 2: ...ended to support or sustain life or for any other application in which the failure of the Samsung product could create a situation where personal injury or death may occur Should the Buyer purchase or use a Samsung product for any such unintended or unauthorized application the Buyer shall indemnify and hold Samsung and its officers employees subsidiaries affiliates and distributors harmless again...

Page 3: ...Mbps ethernet transceriver Section 1 Product Overview introduces a product and describes features PCI system controller application configurations Section 2 External Signals describes external signal pin assignments and signals Section 3 Functional Blocks describes functional block MII PCI bus DMA function block and MAC functional block Section 4 100 Base TX Digital Blocks Section 5 10 Base T Digi...

Page 4: ...PRELIMINARY SPECIFICATION vi KS8910 100 10 Mbps ETHERNET CONTROLLER ...

Page 5: ...s 3 2 Auto Negotiation 3 2 100 Base TX Digital Block 3 3 10Base T Digital Block 3 5 100Base TX and 10Base T Analog Blocks 3 5 Section 4 100 Base TX Digital Blocks Overview 4 1 Physical Coding Sublayer PCS 4 1 physical Medium Attachment Sublayer PMA 4 2 Physical Medium Dependent Sublayer PMD 4 2 Description of operation 4 2 Physical Coding Sublayer PCS 4 4 4B 5B Encoder Decoder 4 4 4B 5B Encoder Tr...

Page 6: ...e 6 6 Clock Recovery 6 6 10Mbit s transmit circuits 6 7 Transmit Wave Shaper 6 7 10MBit s Receive Circuits 6 7 Receiver 6 7 Section 7 Registers Overview 7 1 Register Definitions 7 2 PHY registers 7 3 Base Mode Control register 0 7 3 base mode status register 1 7 5 PHY identifier 1 register 2 7 6 PHY identifier 2 register 3 7 6 Auto negotiation Advertisement Register 4 7 7 Auto negotiation Link Par...

Page 7: ...stics 8 4 Timming 8 5 OSC clock frequency 8 5 MII transmit clock Tolerance 8 5 MII Receive clock Tolerance 8 6 MII 10base T Transmit Timing 8 7 MII 10base T receive Timing 8 8 MII 100Base TX Transmit Timing 8 9 MII 100Base TX receive Timing 8 10 MII Management Interface Timing 8 11 POWER on Reset Timming 8 12 10Base T SQE Heartbeat Timing 8 13 10Base T Jabber Timing 8 14 10Base T Normal Link Pulse...

Page 8: ...r Control Function 5 2 5 2 SQE Function 5 3 5 3 State Diagram of Collision Detection Function 5 4 5 4 State Diagram of Link Integrity Test Function 5 5 6 1 100Mbit s Data Path Block Diagram of KS8910 6 1 6 2 Analog Blocks of KS8910 6 2 6 3 Crystal Oscillator Connection 6 3 6 4 Transmit Twister Pair Driver and Transmit Transformer 6 5 6 5 Receive Buffer Circuit Configuration 6 6 8 1 Clock Frequency...

Page 9: ...s 8 2 8 3 MII Pads Specification 8 3 8 4 100Base TX Transceiver Specification 8 3 8 5 10Base T Transceiver Specification 8 4 8 6 Clock Frequency 8 5 8 7 MII Transmit Clock Tolerance 8 5 8 8 MII Receive Clock Tolerance 8 6 8 9 MII 10Base T Transmit Timing 8 7 8 10 MII 10Base T Receive Timing 8 8 8 11 MII 100Base TX Transmit Timing 8 9 8 12 MII 100Base TX ReceiveTiming 8 10 8 13 MII Management Inter...

Page 10: ...own mode for reduced power consumption Functions provided by the transceiver include encoding and decoding of the serial data stream and delimiters level conversion collision detection signal quality error and link integrity testing jabber control and loopback testing The device also provides outputs for receive transmit collision speed and link test LEDs The new 100 Mbit s implementation of Ether...

Page 11: ...ernet subsystem shown in Figure 1 2 is divided into three sections The system bus interface and Direct Memory Access DMA engine The Media Access Control MAC layer The Physical or Medium Dependent Interface MDI layer The PCI bus interface section contains transmit and receive data buffering DMA control buffering and a register access module buffering The MAC layer consists of transmit and receive b...

Page 12: ...rnet Transceiver Block Diagram Processor Transformer MII 10Base T 100Base TX P C I B U S 10 100Mbps PHY 10 100Mbps MAC KS8920 KS8910 Auto Negotiation 20MHz Link Status Link Control TX MI Station MGM Interface Control Registers Status Registers Power Management Auto neg Arbitration 10 Base T 10 20MHz Fast Ethernet 100 Base TX 25MHz 125MHz Mll Data Interface Driver MLT3 Driver 100RX 10RX Registers R...

Page 13: ...ion Document 802 3u D5 3 June 14 1995 This document has been approved and is being submitted for publication This document has also been submitted and approved as an ISO IEC standard International Standard ISO IEC 8802 3 1993 E ANSI IEEE Std 802 3 information technology Local and metropolitan area networks Part 3 Carrier sense multiple access with collision detection CSMA CD access method and phys...

Page 14: ...al groups Power and ground pins need to be added to this signal list The device will require a 64 pin package This chapter groups the signal definitions by functional area giving each signal s symbolic name full name type and a brief definition The groups are pins for MII Transmit pins for MII Receive pins for MII Station Management pins for Twisted Pair Interface pins for Analog Pins pins for LED...

Page 15: ...nals Transmit Media Independent Interface MII LED Interface Col Receive Media Independent Interface MII MII Management Twisted Pair Interface Analog Pins Controls Tx_clk TxD 3 0 Tx_en Tx_er CrS Rx_clk RxD 3 0 Rx_DV Rx_er MDC MDIO LEDL LEDT LEDR LEDS LEDC TPOP TPON TPOB TPIP TPIN XTAL_OUT XTAL_IN RB SP_SEL FDUPL RESET AN_EN PD ...

Page 16: ...5 34 33 VSSDIG VDDDIG LEDC ID4 LEDL ID3 LEDT ID2 LEDR ID1 LEDS ID0 FDPLX VSSIO VDDIO XTAL_OUT XTAL_IN VSSTXA VDDTXA VSSTXQ VDDTXQ TPIP TPIN SUBANA SP_SEL VDDREF VSSREF RB RBGND AN_EN TPON VSSDRV TPOP SUBDRV TPOB VDDDRV VSSDRV Rx_DV Rx_clk Rx_er Tx_er Tx_clk SUBDIG SUBIO VSSIO VDDIO Tx_en TxD0 TxD1 TxD2 TxD3 Col CrS VSSDIG VDDDIG RxD0 RxD1 RxD2 RxD3 MDC MDIO VSSIO VDDIO VSSRXA VDDRXA PD VSSRXQ VDDR...

Page 17: ...on the rising edge of the Tx_clk TxD 3 0 62 61 60 59 I 5T PD Transmit data Transmit data is aligned on nibble boundaries TxD 0 corresponds to the first bit to transmit on the physical medium and is the LSB of the first byte followed by the fifth bit of that byte during the next clock Tx_en 58 I 5T PD Transmit enable Tx_en provides precise framing for the data carried on TxD 3 0 It is active during...

Page 18: ...ols Rx_er 51 O 5T t s Receive error PHY asserts Rx_er synchronously whenever it detects a physical medium error e g a coding violation The Transceiver asserts Rx_er only when it asserts Rx_DV MII Station Management Signals The next sub table shows the two MII station management signals Use of these signals for configuring the transceiver or negotiating a link protocol is optional MDC 42 I 5T PD Ma...

Page 19: ...ed to send and receive 100Mbit s data on twisted pairs TPOP 21 O TPOP TPON Differential driver outputs to the cable magnetics The on chip driver circuit automatically switches between 10Mbit s and 100Mbit s operation TPON 23 O TPIP 32 I TPIP TPIN Differential receiver inputs from the cable magnetics TPIN 31 I TPOB 19 O Provides a bias for the transmit transformer center tap This bias is about 2 6 ...

Page 20: ...Analog Block VDDRXQ 34 P 3 3V Power Supply for Analog Block VDDDRV 18 P 3 3V Power Supply for Analog Driver Block VSSDIG 1 48 G Ground for Digital Internal Block VSSIO 9 40 56 G Ground for for Digital I O Block VSSTXA 13 G Ground for for Analog Block VSSRXA 38 G Ground for for Analog Block VSSREF 27 G Ground for for Analog Reference Block VSSTXQ 15 G Ground for for Analog Block VSSRXQ 35 G Ground ...

Page 21: ...EXTERNAL SIGNALS KS8910 100 10 Mbps ETHERNET TRANSCEIVER 2 8 Preliminary Spec ver 1 4 MEMO ...

Page 22: ...ily implemented interconnection between the Media Access Control MAC sublayer and Physical PHY layer devices and between PHY layer devices and Station Management The MII interface provides a uniform interface to the Reconciliation Sublayer for all 100Base T physical layer device implementation Services required by the MII include the following Figure 3 1 Functional Block Diagram of KS8910 Auto Neg...

Page 23: ... the Transceiver chip Auto Power Down Function 10 100Mbps CONTROL REGISTERS STATUS REGISTERS The control and status registers set are used to control and monitor the 10Base T 100Base TX Transceiver chip and can be accessed through the MII management interface The management interface consists of a pair of signals which physically transport the management information across the MII a frame format a...

Page 24: ...er continues to replace subsequent 4B codes with corresponding 5B symbols At the end of the transmit data packet the symbol encoder injects the T R symbol pair indicating end of frame The symbol encoder continuously injects IDLE symbols into the transmit data stream until the next transmit data packet is detected Parallel to Serial Block The Parallel to Serial Block performs Serialization of code ...

Page 25: ...his block receives scrambled transmit data stream and NRZI encodes the data in order to comply with the TP PMD standard for 100Base TX transmission over Category 5 unshielded twisted pair cable Serial to Parallel Block The function of the Serial to Parallel block is to provide Serial to Parallel conversion of code groups for reception from the underlying Physical Medium attachment sublayer 5B 4B T...

Page 26: ...e the 10BASE T Ethernet Interface performs all required MAU functions defined by the IEEE 802 3 10BASE T specification such as collision detection link integrity testing signal quality error messaging jabber control and loopback The 10Base T digital block also provides repeater clients an indication that a carrier event has been sensed and an indication if it is deemed in error A carrier event is ...

Page 27: ...lizer compensates for amplitude and phase variations introduced by twisted pair cable The equalizer compensates the transfer functions of cables over the range of 0 meters to 100 meters The equalization circuit also corrects for baseline wander that is introduced by AC coupling transformers The equalization circuits require no off chip components or external adjustments Signal Dectector The Signal...

Page 28: ...PMD Revision 2 2 1 March 1995 specification PHYSICAL CODING SUBLAYER PCS The PCS interface is the Media Independent Interface MII which provides a uniform interface to the Reconciliation Sublayer for 100Base TX of the KS8910 The KS8910 s PCS realizes the following functions Encoding decoding of MII data nibbles to from 5 bit code groups 4B 5B Generating Carrier Sense and Collision Detect indicatio...

Page 29: ...ZI format Furthermore the PMD recovers the clock from the incoming data bits The PMD block is an Analog Block DESCRIPTION OF OPERATION Transmit operation Data for transmission is received in nibbles by the PCS over the MII The PCS then converts each nibble into a 5 bit code group which is serialized and forwarded to the PMA The PMA scrambles the serialized bit stream and converts it from NRZ to NR...

Page 30: ...CS_TRANSMIT_BITS PMA_TX PCS_TRANSMIT TXD 3 0 TX_EN TX_ER 6 4 5 TX_CLKOUT PCS_CARSM CARRIER SENSE OUTPUT 1 TRANSMITTING 1 RECEIVING LINK_STATUS 1 0 2 2 2 PCS_RECEIVE PMA_LMSM LINK MONITOR SIGNAL_STATUS LINK_CONTROL 1 0 0 1 RX_DOUT 3 0 RX_DVOUT RX_EROUT RX_CLKOUT 4B 5B Decoder Receive State Machine 7 4 4 4 10 25MHz 125MHz 9 0 RX_BIT 9 0 10 got_code PCS_RXBITSSM PCS_RECEIVE_BITS PMA_RXSM NRZI æNRZ NR...

Page 31: ...ded into data nibbles which are transferred to the MAC through the MII Because of the different wire bit rates of data in parallel form and serial form two different clocks are required The encoding takes place in the 25 MHz clock domain while all other functions require a 125 MHz clock A detailed description of each functional block is given the following sub sections 4B 5B ENCODER DECODER The ma...

Page 32: ...F Data IDLE Undefined I 11111 Idle Used as inter steam fill code CONTROL 0101 J 10001 First symbol of Start of Stream Delimiter SSD1 0101 K 01101 Last symbol of Start of Stream Delimiter SSD2 undefined T 00111 First symbol of End of Stream Delimiter ESD1 undefined R 00111 Last symbol of End of Stream Delimiter ESD2 INVALID undefined H 00100 Transmit Error used to force signal error undefined Inval...

Page 33: ...ecoder converts the received 5 bit code groups into nibbles In general this is a trivial translation process However preamble bits have to be substituted for the first two code groups of a packet the Start of Frame Delimiter The 5B 4B Decoder scans the incoming bit stream for the SSD and locks to it After locking to the incoming bit stream each 5 bit code group is translated into a nibble accordin...

Page 34: ... 1 COL receiving TXbits ssd1 sent_code TX_EN TX_ERR transmitting 1 COL receiving TXbits ssd2 sent_code TX_ERR transmitting 1 COL receiving TXbits ssd2 sent_code TX_ERR transmitting 1 COL receiving TXbits halt sent_code transmitting 1 COL receiving TXbits halt sent_code TX_EN TX_ERR transmitting 1 COL receiving TXbits encode TXD sent_code TX_EN TX_ERR transmitting 0 TXbits esd1 sent_code TX_EN COL ...

Page 35: ...9 2 RXbits 0 RXbits idle SSD2 receiving 1 RX_DV 1 RX_ER 0 RXD 4 h5 INIT_RBITS 0 RXbits SSD1 SSD2 receiving 1 RX_DV 0 RX_ER 1 RXD 4 hE INIT_RBITS 0 RXbits 9 5 SSD1 RXbits 4 0 SSD2 receiving 1 RX_DV 1 RX_ER 0 RXD 4 h5 INIT_RBITS 0 got_code receiving 1 RX_DV 0 1 RX_ER 0 1 RXD decode RXbits 9 5 4 h0 got_code RXbits idle idle RXbits ESD1 ESD2 receiving 1 RX_DV 0 1 RX_ER 0 1 RXD 4 h0 INIT_RBITS 0 1 got_...

Page 36: ...es a serial bit stream from the PMA and coverts it into a stream of 5 bit code groups in parallel form which is then forwarded to the Decoder Before the conversion can take place the Encode has to lock to the incoming serial bit stream The Encoder provides the Parallel Converter with an align signal after it has discovered the Start of Stream Delimiter The parallel conversion takes place in the 12...

Page 37: ...11 X n 9 modulo 2 The scrambler shall generate the specified non zero key stream whenever the Active Output Interface is required to transmit a scrambled data stream The key steam sequence can be generated by an 11 bit Linear Feedback Shift Register LFSR whose input bit is the exclusive OR of its 11th and 9th previous bits and which contains at least one non zero bit The functional diagram for the...

Page 38: ...m added to those bits While the descrambler is synchronized error free bits in the cipher text stream decode as error free bits in the plain text stream and errored bits in the cipher text stream decode as errored bits in the plain text stream The descrambler shall acquire synchronization on receipt of 60 consecutive error free cipher text bits of the Idle Line State ILS pattern while SIGNAL_DETEC...

Page 39: ...ation The Link Monitor process monitors SIGNAL_STATUS and sets link_status to FAIL whenever SIGNAL_STATUS is OFF or when Auto negotiation sets link_control to DISABLE The link is deemed to be reliably operating when SIGNAL_STATUS has been continuously ON for a certain period of time If so qualified Link Monitor sets link_status to READY in order to synchronize with Auto negotiation Auto negotiatio...

Page 40: ...it sees a ONE the output will shift at the beginning of the next bit period This transition can be high to low or low to high If the converter module sees a ZERO the output will remain unchanged for another bit period The NRZI to NRZ module converts the signal from NRZI to NRZ as follows If the input remains unchanged from 1 bit period then the converter module will output a ZERO If there is a cha...

Page 41: ...ugh a resume is given just below A detailed description of this part of the circuitry can be found in chapter 6 of this document In the transmit direction the serial data stream is converted from NRZI to MLT 3 In the inbound direction the DC level of the signal is first restored then it runs through an equalizer and finally it gets converted from MLT 3 to NRZI format Then the clock as well as data...

Page 42: ...LS MAU mode In the integrated PLS MAU mode the 10BASE T Ethernet Interface performs all required MAU functions defined by the IEEE 802 3 10BASE T specification such as collision detection link integrity testing signal quality error messaging jabber control and loopback TRANSMIT FUNCTION The 10BASE T transceiver receives NRZ data from the controller at the TXD input see 10 100 Mbit s transceiver bl...

Page 43: ...Timer 0 jc_set_TxMaxTimer 1 jc_en_TxMaxTimer 1 jc_set_sr_jabberStatus 1 jc_dis_XMIT 0 jc_ci_sqe 0 jc_set_TxMaxTimer 0 jc_clr_TxMaxTimer 0 jc_en_TxMaxTimer 0 jc_set_sr_JabberStatus 0 jc_set_UnJabberStatus 0 jc_set_UnjabberStatus 0 jc_set_UnJabberTimer 0 jc_en_unJabberTimer 0 jc_dis_XMIT 1 jc_dis_LPBK 1 jc_ci_sqe 1 jc_set UnjabTimer 1 jc_en_UnjabTimer 1 jc_dis_XMIT 1 jc_dis_LPBK 1 jc_ci_sqe 1 jc_set...

Page 44: ...TPI circuit inputs falls below 75 of the threshold level unsquelched for eight bit times typical the 10BASE T transceiver receive function enters the idle state If the polarity of the TPI circuit is reversed the 10BASE T trans ceiver detects the polarity reversal and reports it via the PLR output The 10BASE T transceiver automatically cor rects reversed polarity POLARITY REVERSE FUNCTION The 10BAS...

Page 45: ...OL pin If the TPI circuit becomes active while there is activity on the TPO circuit the TPI data is passed to the back end over the RXD circuit disabling normal loopback Figure 5 3 is a state dia gram of the 10BASE T transceiver collision detection function Figure 5 3 State Diagram of Collision Detection Function cid_COL collision detected CI collision Input CID_IDLE_w Reset or default CID_IDLE CI...

Page 46: ...ional forced loopback functions controlled by LBK BMCR Register Bit When the TP port is selected and LBK 1 TP loopback is forced overriding collisions on the TP circuit When LBK 0 normal loop back is in effect LINK INTEGRITY TEST Figure 5 4 is a state diagram of the 10BASE T Transceiver Link Integrity test function The link integrity test is used to determine the status of the receive side twisted...

Page 47: ...10BASE T DIGITAL BLOCKS KS8910 100 10 Mbps ETHERNET TRANSCEIVER 5 6 Preliminary Spec ver 1 4 MEMO ...

Page 48: ...de a receive buffer an adaptive equalizer a baseline restore circuit and clock recovery In addition the receive circuit detects the presence of on the receive twisted pair and supplies status signals to the autonegotiation circuit indicating lock detect and signal detect A few board level passive components are required to support the analog circuits These components include a 25 MHz crystal a ref...

Page 49: ...e receive twisted pair and supplies status signals to the auto negotiation circuit indicating lock detect and signal detect A few external components are required to support the analog circuits These components include a 25MHz oscillation circuit and a current reference bias circuit 100MBIT S TRANSMIT CIRCUITS The 100 Mbit s Transmit analog block generates the clocks required for data transmission...

Page 50: ... to the oscillator circuit is shown in Figure 6 3 A 25 MHz 50ppm fundamental mode parallel resonant crystal should be used The values of the loading capacitors should be adjusted to match the recommended loading for the crystal used The recommended crystal is loaded with 15pF capacitors as shown in Figure 6 3 The external crystal and loading capacitors are connected between the XTAL_IN and XTAL_OU...

Page 51: ... ratio of 1 second coil first coil However turns ratios lower than 1 second coil firstcoil will not enable full 10 Mb s voltage swing and higher turns ratios will result in higher power dissipation A Pulse Valor XFMRS s transformer can meet the application requirements Please refer to Application Notes The 100 Mbit s driver is connected in parallel with the 10 Mbit s driver to the TPOP and TPON pi...

Page 52: ...CUITS The receive circuits include a receive buffer an adaptive equalizer a baseline restore circuit and clock recovery The outputs of the analog receive block are data on 100RXD and a recovered clock on 100RXClk The presence of a receive signal is signaled as RX Signal Detect The clock recovery lock detect is signaled on RXClk Lock RECEIVER BUFFER A receive buffer is used to isolate the internal ...

Page 53: ...STORE Baseline wander caused by long run lengths in data is compensated by the baseline restore circuit Run lengths as long as 57 bits are possible on 100Base TX It is impractical to build transformers that display droop times long enough to recover data of this run length The baseline restore circuit uses a nonlinear signal processing technique to restore data signals that have drooped due to exc...

Page 54: ...nchester encoded bit stream and converts it into a waveshape that fits the IEEE 802 3 template refer to IEEE802 3u 10MBIT S RECEIVE CIRCUITS The receive circuits include a receive buffer an adaptive equalizer a baseline restore circuit and receive clock recovery The outputs of the analog receive block are data on 10RXD and a recovered clock on 20RXClk The presence of a receive signal is signaled a...

Page 55: ...ne termination is performed by the circuit shown in Figure 6 5 RECEIVE CLOCK RECOVERY 20MHZ DPLL An on chip frequency synthesis PLL recovers a 20MHz clock using the frequency reference from receiving data The PLL uses digital techniques to create the optimum clock for re timinig the received data ...

Page 56: ...er BMCR The software reset the Reset bit in BMCR will reset the status registers and all the state machines of the 10Base T 100Base TX Transceiver to their default values All other registers will maintain their pre reset values All required changes of the control registers necessary to obtain a wanted mode of operation should be carried out before the Reset bit is activated In order to reset all t...

Page 57: ...r Ability Register 5 05h 0000_0000_0000_0001 E ANLPAR NEXT PAGE 0000_0000_0000_0000 E ANER Auto Negotiation Expansion Register 6 07h 0000_0000_0000_0100 E ANNPTXR Auto Negotiation Next Page Transmit Register 7 07h 0000_0000_0000_0000 E Reserved 08h 0fh E B10CR 10Base T Control Register 16 10h 1110_0000_0010_0000 E TXCR 100Base_TX Control Register 17 11h 0000_0000_0000_0000 E PAR PHY Address Regist...

Page 58: ...e cleared This bit is self clearing and will return a value of 1 until Auto Negotiation is initiated by KS8925 whereupon it will self clear Operation of the Auto Negotiation process is not affected by the management entity clearing this bit Isolate Isolate 0 Normal operation default 1 Internal MII Isolate High Impedence When this bit is set the PHY Layer does not respond to TXD 3 0 TX_EN and TX_ER...

Page 59: ...n enables MII transmit data to be routed to the MII receive data path This loopback will go through the PMA and the RX clock will be TX clock PhyRst PHY Reset 1 KS8910 reset 0 Normal operation default This bit set the status registers and all of the states of PHY to their default value This bit which is self clearing returns a value of zero until the reset process is complete ...

Page 60: ... remain cleared until it is read via the management interface After the read this bit will latch the XCVR link status at the end of the read AN_Abt Auto Negotiation Ability 1 Auto negotiation Available permanently set 0 Auto negotiation not available Rmt_Fault Remote Fault 1 Remote fault detected 0 No remote fault detected default This bit is cleared on read When the RF bit in the received base Li...

Page 61: ... 1111 0000 03h 15 10 9 4 3 0 OUI_LSB VNDR_MDL MDI_REV MDI_REV Model Revision Number Four bits of vendor model revision number mapped to bit 3 to 0 most significant bit to bit 3 Initial value 0000 VNDR_MDL Vendor Model Number Six bits of vendor model number mapped to bits 9 to 4 most significant bit to 9 The VNDR_MDL and MDI_REV should be programmed by the system manufacturer to reflect the product...

Page 62: ...up 100Base TX Half Duplex 1 100Base TX HALF DUPLEX is supported by the KS8910 0 100Base TX HALF DUPLEX is not supported by the KS8910 100FullDup 100Base TX Half Duplex 1 100Base TX FULL DUPLEX is supported by the KS8910 0 100Base TX FULL DUPLEX is not supported by the KS8910 Rmt_Fault Remote Fault 1 Advertised that this device has detected a Remote Fault 0 Not Remote Fault detected ACK Acknowledge...

Page 63: ...is not supported by the Link Parter RF Remote Fault If set 1 a Remote Fault is detected by Link Partner ACK Acknowledge If set 1 Link Partner acknowledge the Reception of ability data word NP Next Page Indication If set 1 Link Parter supports Next page function 05h 15 14 13 12 11 10 0 NextPg ACK MsgPg ACK2 Tog Pg_Code Pg_Code Page Code If the MsgPg 1 this field will be interpreted as the Message P...

Page 64: ...otiation Next Page Transmit register 0 New Link Code Word has not been received NP_Able Next Page Able This status bit indicates if this XCVR supports Next Page negotiation This XCVR is capable of supporting the Next Page negotiation 1 This XCVR is Next Page Able Permanently Set 0 This XCVR is not Next Page Able LP_NP_Able Link Partner Next Page Able This status bit indicates if the Link Partner s...

Page 65: ... of the Toggle bit in the Link Code Work sent by this KS8910 is 0 0 Previous value of the Toggle bit in the Link Code Work sent by this KS8910 is 1 ACK2 Acknowledge 2 1 This has ability to comply with the message 0 This has not ability to comply with the message MsgPg Message Page 1 Message Page 0 Unformatted Page ACK2 Acknowledge 1 This KS8910 acknowledges the Reception of a Link Code Word 0 This...

Page 66: ...imer TestMode 0 800 ms ticks TestMode 1 4 ms ticks To get out of the test mode the programmer has to clear this TstMode PLR Link Polarity Reverse Enable 1 Enable Link Polarity Reverse function 0 Disable Link Polarity Reverse function DLPBK Data Loopback If set start 10Base T Data Loop Back SQE_En SQE Test Enable 1 Enable SQE Test Function 0 Disable SQE Test Function default When this KS8910 is con...

Page 67: ... 0 Use only IDLE to achieve Descrambler synchronization DTMode Descrambler Test Mode 1 Descrambler Lock timeout value is equal to 260 bits 0 Descrambler Lock timeout value is equal to 2 17 bits 1 048 ms BP_SCR Bypass Scrambler 1 Scrambler and descrambler functions bypassed 0 Normal Scrambler Descrambler operation BP_4B5B Bypass 4B5B 1 4B 5B encoder and 5B 4B decoder functions are bypassed 0 Normal...

Page 68: ...e 26 0 MPTBLE0 15 0 MPTBLE1 10 0 14h 15 14 13 12 11 10 0 Iadj_UP Iadj_S1 IadjS0 SS_Mux Sel_BG Map_Table Iadj_UP PrefilterCnt Data Input Signal comparing level control RX path data jitter control The initial value of tIadj_S1 15 13 is 0 Iadj_S1 Iadj_S0 100M Path Data Input Signal comparing level control The initial value of tIadj_S1 ladj_S0 is 00 SS_Mux Select SS Mux Select SS Mux for PRF Sel_BG Se...

Page 69: ...1 PQ value select 0 Normal operatoin value select PDDRV Power down TXPLL Power Down for DRIVER PDTP Power down TXPLL Power Down for TXPLL PDRP Power down RXPLL Power Down for RXPLL PDRE Power down Reference Power Down for Reference and X tal PDPF Power down Prefilter Power Down for bias bulk of prefilter PDR Power down Reference Power Down for reference PDSG Power down Signal Dectect Power Down fo...

Page 70: ...output value PG PA QI QA 18h 15 14 13 12 11 10 9 8 0 XMT RCV COL PLR JAB LNKST FD Reserved FD Full Duplex 1 Full Duplex 0 Half Duplex LNKST Link Status 1 10Base T link is up 0 10Base T link is down JAB Jabber Detected 1 jabber condition detected 0 no jabber condition detected PLR Polarity Reverse Detected 1 Polarity Reverse Detected 0 Polarity Reverse not Detected COL Collision Detected 1 Collisio...

Page 71: ...3 12 11 10 9 8 0 XMT RCV COL Resreved LNKST FD Reserved FD Full Duplex 1 Full Duplex 0 Half Duplex LNKST Link status 1 100Base TX link is up 0 100Base TX link is down COL Colision Detected 1 Collision detected 0 Collision not detected RCV Receive Active 1 Active Receive 0 Transmit IDLE XMT Transmit Active 1 Active Transmit 0 Transmit IDLE ...

Page 72: ...1 4 8 ELECTRICAL CHARACTERISTICS This chapter describes the electrical characteristics of KS8910 100 10Mbps Ethernet Transceiver The information is presented according to the following table of contents Absolute Maximum Ratings Recommaned Operating Ranges D C Electrical Characteristics Timming ...

Page 73: ...ximum Ratings TA 25 C Parameter Symbol Min Max Unit Supply Voltage VDD GND 0 3 3 8 V Operating Tempatature TOP 0 70 C Storage Temperature TSTG 65 150 C Table 8 2 Recommended Operating Conditions Parameter Symbol Conditions Min Typ Max Unit Operating Voltage VDD 3 1 3 3 3 5 V Supply Current 100Base TX I100TX 180 mA 10Base T I10T 200 mA Power Down Mode IPD 300 uA Auto Negotiation IAN 300 mA Ambient ...

Page 74: ...ter Symbol Conditions Min Typ Max Unit Input Low Voltage VIL 0 8 V Input High Voltage VIH 2 0 V Ouput Low Voltage VOL IOL 6mA 0 4 V Ouput High Voltage VOH IOH 6mA 2 4 V VDD Supply Current IDD 100 uA PowerDown Current IPD Note 1 uA Input Low Current IIL 10 10 uA Input High Current IIH 10 10 uA Table 8 4 100Base TX Transceiver Specification Parameter Symbol Conditions Min Typ1 Max Unit Peak Differen...

Page 75: ...transformer 4 After line model specified by IEEE802 3 for 10Base T Table 8 5 10Base T Transceiver Specification Parameter Symbol Conditions Min Typ1 Max Unit Differential Squelch Threshold VTSQ_I Normal Threshhold NTH 1 300 585 mV VTSQ_O Normal Threshhold NTH 0 180 461 mV Link Transmit Period TLTP Note2 8 24 ms TPOP TPON Output Voltage Template Note2 Shown in figure 9 1 9 2 9 3 based upon IEEE Sta...

Page 76: ...gure 8 1 Clock Frequency Timing Diagram Table 8 6 Clock Frequency Symbol Conditions Min Typ Max Unit t1 Clock Freq Dudy Cycle 45 50 55 t2 Clock Period 40 ns Figure 8 2 MII Transmit Clock Tolerance Timing Diagram Table 8 7 MII Transmit Clock Tolerance Symbol Conditions Min Typ Max Unit t1 Tx_clk Duty Cycle 100M 35 60 65 10M 35 50 65 t2a Tx_clk Period 100Base TX MII Interface 40 ns t2b Tx_clk Period...

Page 77: ... RX_clk Duty Cycle switching point is 50 if VDD Figure 8 3 MII Receive Clock Tolerance Timing Diagram Table 8 8 MII Receive Clock Tolerance Symbol Conditions Min Typ Max Unit t1 Rx_clk Duty Cycle 100M 35 60 65 10M 35 50 65 t2a Rx_clk Period 100Base TX MII Interface 40 ns t2b Rx_clk Period 10Base T MII Interface 400 ns t2 t1 RX_clk ...

Page 78: ... Timing Diagram Table 8 9 MII 10Base T Transmit Timing Symbol Conditions Min Typ Max Unit t1 TxD Tx_en Tx_er Setup to Tx clk rise 10 ns t2 TxD Tx_en Tx_er Hold from Tx clk rise 10 ns t3 Tx_en sampled to CrS asserted 4 8 us t4 Tx_en sampled to CrS de asserted 2 0 us t5 Tx_en sampled to TPO out Tx latency 1 0 us t1 Tx_clk t3 TxD Tx_en Tx_er t2 t4 t5 CrS TPOP ...

Page 79: ... TPI in to RxD out Rx latency 4 us t2 RxD Rx_DV Rx_er Setup to Rx clk rise 10 ns t3 RxD Rx_DV Rx_er Hold form Rx clk rise 10 ns t4 CrS asserted to RxD Rx_DV Rx_er asserted 0 us t5 RxD Rx_DV Rx_er de asserted to CRS de asserted 0 us t6 TPIP in to CRS asserted 0 4 us t7 TPIP quiet to CRS de asserted 0 1 0 us t8 TPIP in to COL asserted 0 1 7 us t9 TPIP quiet to COL de asserted 0 1 0 us Rx_clk t4 RxD ...

Page 80: ...smit Timing Diagram Table 8 11 MII 100Base TX Transmit Timing Symbol Conditions Min Typ Max Unit t1 TxD Tx_en Tx_er Setup to Tx clk rise 25 ns t2 TxD Tx_en Tx_er Hold from Tx clk rise 25 ns t3 Tx_en sampled toTPO out Tx latency 50 ns t4 Tx_en sampled to CRS asserted 10 ns t5 Tx_en sampled to CRS de asserted 50 ns t1 Tx_clk t2 t3 t4 t5 Tx_en TxD 3 0 TPOP CrS ...

Page 81: ...ol Conditions Min Typ Max Unit t1 RXD RX_EN RX_RX Setup to RX CLK rise 10 ns t2 RXD RX_EN RX_ER Hold from RX CLK rise 10 ns t4 CRS asserted to RX_DV asserted 160 ns t6 Receive start of J to CRS asserted 80 ns t7 Receive start of T to CRS de asserted 90 ns t8 Receive start of J to CRS asserted 0 15 19 20 ns t9 Receive start of T to CRS de asserted 13 23 27 28 ns TPIP t1 t2 CrS RxDV RxD 4 0 Rx_clk t...

Page 82: ...MII Management Interface Timing Diagram Table 8 13 MII Management Interface Timing Symbol Conditions Min Typ Max Unit t1 MDC Minimum High Time 160 ns t2 MDC Minimum Low Time 160 ns t3 MDC Period 400 ns t4 MDC rise to MDIO valid 0 300 ns t5 MDIO Setup to MDC 10 ns t6 MDIO Hold after MDC 10 ns t1 t2 MDC MDIO output t3 t4 MDC MDIO Input t5 t6 ...

Page 83: ...s ETHERNET TRANSCEIVER 8 12 Preliminary Spec ver 1 4 POWER ON RESET TIMMING Figure 8 9 Power On Reset Timming Diagram Table 9 14 Power On Reset Timming Symbol Conditions Min Typ Max Unit tR Power_On to normal operation 3 0 us POR tR VDD VDD 2 0V ...

Page 84: ...eliminary Spec ver 1 4 10BASE T SQE Heartbeat TIMING Figure 8 10 10Base T SQE Heartbeat Timing Diagram Table 8 15 10Base T SQE Heartbeat Timing Symbol Conditions Min Typ Max Unit t1 COL SQE Delay after Tx_en off 1 2 us t2 COL SQE Pulse duration 1 2 us Tx clk t1 t2 Tx_en Ready ...

Page 85: ...ET TRANSCEIVER 8 14 Preliminary Spec ver 1 4 10BASE T JABBER TIMING Figure 8 11 10Base T Jabber Timing Diagram Table 8 16 10Base T Jabber Timing Symbol Conditions Min Typ Max Unit t1 Maximum Transmit time 1002 ms t2 Unjab time 500 ms Tx_en Col t1 t2 TxD ...

Page 86: ...y Spec ver 1 4 10BASE T NORMAL LINK PULSE TIMING Figure 8 12 10Base T Normal Link Pulse Timing Diagram Table 8 17 10Base T Normal Link Pulse Timing Symbol Conditions Min Typ Max Unit t1 Normal Link Pulse Width 10Base T 100 ns t2 COL Heartbeat assertion duration 8 10 24 ms TPOP t1 t2 ...

Page 87: ...gram Table 8 18 10Base T Jabber Timing Symbol Conditions Min Typ1 Max Unit t1 Clock Data pulse width 100 ns t2 Clock pulse to Data pulse timing 64 us t3 Clock pulse to Clock pulse 128 us t4 FLP Burst width 2 ms t5 FLP burst to FLP burst timing 8 14 24 ms t6 Number if Clock Data pulses in a burst 17 33 pulses TPOP t1 t2 TPOP t1 t3 t4 t5 FLP Burst FLP Burst FLP Burst Clock Pulse Data Pulse Data Puls...

Page 88: ...ND 34 3 3V 27 SW1 0 Ù C22 10 Þ C23 0 1 Þ C26 0 1 Þ R13 100 C18 0 1 Þ C24 0 1 Þ C17 10 Þ R12 200 C3 22 Þ SW5 0 C15 0 1 Þ C19 17 5 SW11 0 R21 1 5 Ú R20 1 5 Ú R19 1 5 Ú C10 0 1 Þ C2 22 Þ L2 0 068 Þ C12 0 1 Þ C20 17 5 R11 25 Ú L1 0 068 Þ C14 0 1 Þ SW12 0 Ù SW6 0 SW10 0 C13 10 Þ C28 0 1 Þ C31 0 1 Þ C6 0 1 Þ C5 0 1 Þ C16 0 1 Þ C29 0 1 Þ C11 0 1 Þ C7 0 1 Þ C21 0 1 Þ C27 0 1 Þ C4 0 1 Þ C30 0 1 Þ C25 0 1 Þ...

Page 89: ...APPLICATION NOTE KS8910 100 10 Mbps ETHERNET TRANSCEIVER 9 2 Preliminary Spec ver 1 4 MEMO ...

Page 90: ...er 1 4 10 MECHANICAL DATA PACKAGE DIMENSION 64 QFP 1414 PACKAGE Figure 10 1 KS8910 Package Dimension 64 QFP 1414 Type 17 20 0 30 14 00 0 20 17 20 0 30 14 00 0 20 1 64 0 80 0 35 0 10 0 10MAX 2 60 0 10 0 10MAX 0 05MIN 0 80 0 20 0 1 5 0 05 0 8 Demension in milimeter 1 00 0 10 2 80MAX ...

Page 91: ...MECHANICAL DATA KS8910 100 10 Mbps ETHERNET TRANSCEIVER 10 2 Preliminary Spec ver 1 4 MEMO ...

Page 92: ...k Protocol See AnyLAN AnyLAN Also 100BASE VG AnyLAN 100 Mbit s alternative to Ethernet and Token Ring Also IEEE 802 12 ADSL Asymmetric Digital Subscriber Lines From Bell Communications Research Inc Uses as few as four wire twisted pair Alignment error When the Mac receives a frame that is not an integer number of bytes long and the CRC is invalid Synonym framing error See also dribble ARP Address ...

Page 93: ...ble carry DS1 rate and format between COs DS2 6 312 Mbit s asynchronous rate Four DS1 signals DS3 44 736 Mbit s asynchronous rate 28 DS1 signals T3 equipment and cable carry DS3 rate and format between COs DMA Direct Memory Access Dribble When the Mac receives a frame that is not an integer number of bytes long Dribble produces an alignment error when the CRC is invalid DTE Data Terminal Equipment...

Page 94: ...9 1 See JTAG IEEE 802 12 100 Mbit s standard based on demand priority Also 100BASE VG or AnyLAN IEEE 802 3 Information technology Local and metropolitan area networks Part 3 Carrier sense multiple access with collision detection CSMA CD access method and physical layer specifications International Standard ISO IEC 8802 3 1993 E ANSI IEEE Std 802 3 1993 Edition July 8 1993 Also Ethernet IEEE 802 4 ...

Page 95: ... 00 00 There are two kinds of multicast address a Multicast group address An address associated by higher level convention with a group of logically related stations b Broadcast address A distinguished predefined multicast address that always denotes the set of all stations on a given local area network Multicast group address An address associated by higher level convention with a group of logica...

Page 96: ...equest message PCMCIA Personal Computer Memory Card International Association Also People Can t Memorize Computer Industry Acronyms PDU Protocol Data Unit in ATM PHY Physical Layer Entity as defined in the 802 Architecture and Overview Standard The word PHY is used to denote the set of functions associated with a physical layer protocol PLS Physical Signalling layer of LAN CSMA CD See OSI PMA Phys...

Page 97: ...cation program provided by almost every TCP IP implementation SNMP Simple Network Management Protocol Allows a TCP IP host to query other nodes for network related statistics and error conditions Sonet Synchronous Optical Network ANSI U S fiber optic transmission standard See also SDH SonicTM National Semiconductor Corporation s DP83932B Systems Oriented Network Interface Controller Spanning tree ...

Page 98: ... facility for a user process Uses IP Part of the TCP IP protocol suite Universal address An Ethernet address whose second bit transmitted used to distinguish between locally or globally administered addresses is set to 0 indicating a globally administered or U universal address If an address is to be assigned locally this bit shall be set to 1 Note that for the broadcast address this bit is also a...

Page 99: ...A 8 APPENDIX KS8910 100 10 Mbps ETHERNET TRANSCEIVER Preliminary Spec ver 1 4 NOTES ...

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