Renesas H8 Series, User Manual

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8.2 Notes on Usage of the H8/3664 E6000 Emulator
There are the following notes on usage of the emulator.
8.2.1 I/O Register
In the E6000 emulator, one evaluation chip emulates several types of MCU. Therefore, there are some
differences in I/O registers between an actual MCU and the emulator. Note these differences when accessing the
I/O registers.
I/O port is in the input state at default. The I/O register contents indicate the emulator port status. When the user
system interface cable is not connected, the read value is 1 due to pull-up resistors.
In the emulator, accesses to the following registers for controlling the flash memory are invalid.
•
Flash memory control register 1 (FLMCR1: H'FF90)
•
Flash memory control register 2 (FLMCR2: H'FF91)
•
Flash memory power control register (FLPWCR: H'FF92)
•
Block register 1 (EBR1: H'FF93)
•
Flash memory enable register (FENR: H'FF9B)
Note: The addresses indicate the lower 16 bits.
(1) Warnings that Apply to H8/3664 Group Programming
(a) The description given in the hardware manual is “Initial value: 1. Reserved. These bits are always read as
1”. However, the description in the emulator manual is “Always specify 0. These bits are always read as
the specified values”.
Table 8.14 Differences between the H8/3664 Group Products (1)
Target Address Register Name Bits
H’FFE0 Port mode register 1 3 and 2
(b) The description given in the hardware manual is “Initial value: 0. Reserved. These bits are always read as
0”. However, the description in the emulator manual is “Always specify 0. These bits are always read as
the specified values”.
Table 8.15 Differences between the H8/3664 Group Products (2)
Target Address Register Name Bits
H’FFE1 Port mode register 5 7 and 6
H’FFF9 Module standby control register 1 7
(c) The description given in the hardware manual is “Reserved”. However, the description in the emulator
manual is “Always specify 0. These bits are always read as the specified values”.
Table 8.16 Differences between the H8/3664 Group Products (3)
Target Address Register Name Bits
H’FFE2 Port mode register 3 7 to 3
H’FFF5 Interrupt enable register 2 7 to 5
H’FFFA Module standby control register 2 7 to 0
H’FFFB Module standby control register 3 0