CHAPTER 5 USAGE
User’s Manual S19262EJ3V0UM
46
5.2 Baud
Rate
Setting
A baud rate is determined according to the settings for serial clock input and the DLM and DLL registers. EM1
assumes that the serial clocks below are input.
Clock frequencies can be set individually. For details about clock settings, see the
Multimedia Processor for
Mobile Applications - System Control/General-Purpose I/O Interface User's Manual (S19265E)
.
Clock
Frequency
[Hz]
Clock Source
Baud Rate
(bps)
Error
Range
DLMR
DLLR
Actual Baud
Rate (bps)
Error
(%)
229.376 M
PLL3
2400
±4 23
85
2400.13394
0.0055807
4800
11
171
4799.46435
0.011159
9600
5
213
9602.14334
0.0223264
19200
2
235
19191.4324
0.044623
38400
1
117
38434.3164
0.0893655
57600
0
249
57574.2972
0.044623
115200
0
124
115612.903
0.3584229
Clock
Frequency
[Hz]
Clock Source
Baud Rate
(bps)
Error
Range
DLMR
DLLR
Actual Baud
Rate (bps)
Error
(%)
7.168 M
PLL3/32
2400
±4
0
187
2395.72193
0.178253
4800
0
93
4817.2043
0.3584229
9600
0
47
9531.91489
0.70922
19200
0
23
19478.2609
1.4492754
38400
0
12
37333.3333
2.777778
57600
0
8
56000
2.777778
115200
0
4
112000
2.777778
5.3 Notes on Use of FIFOs
UART and the internal bus communicate via a 2-byte interface, so the FIFOs can be read or written at the same
time in 2-byte units, but note the following:
(1) An overrun error occurs when 2-byte data is written in response to a DMA request when only 1 byte of space is
available in the transmit FIFO in the DMA mode 1.
(2) When a reception timeout event occurs in DMA mode 1 while the timeout interrupt is enabled (bit 4 of the IER
register = 0), the host cannot determine whether the request is issued due to a timeout event or the trigger
level. As a result, if 2 bytes are read in response to a DMA request, a FIFO underrun error occurs.
