CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
16
3.2.3 Interrupt identification register
This register (IIR: 5000_0008H (UART0), 5001_0008H (UART1), 5002_0008H (UART2)) is used to identify
interrupt sources.
The FIFO operating mode and interrupt sources can be checked by reading this register.
When multiple interrupts sources are generated, the interrupt source that has the highest priority is output to this
register.
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
FIFOs Enabled[1:0]
64 Byte FIFO
Enabled
Reserved Interrupt
ID[3:0]
Name R/W
Bit
After
Reset
Function
Reserved
R
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
FIFOs Enabled[1:0]
R
7:6
00b
Indicates the FIFO operating mode.
00b: Non-FIFO mode (16450 mode)
11b: 16-byte/64-byte FIFO mode (See bit 5.)
64 Byte FIFO Enabled
R
5
0
Indicates the FIFO operating mode. This bit is enabled when bits 7
and 6 are set to 11b.
0: 16-byte FIFO mode (16550 mode)
1: 64-byte FIFO mode
Reserved
R
4
0
Reserved. When this bit is read, 0 is returned.
Interrupt ID[3:0]
R
3:0
0001b
Among the interrupts that have occurred, these bits indicate the ID of
the interrupt source that has the highest priority.
Table 3-1. FIFO Operating Mode (Bits 7 to 5)
Bits 7 to 5
FIFO Operating Mode
000
Non-FIFO mode (16450 mode)
110
16-byte FIFO mode (16550 mode)
111 64-byte
FIFO
mode
