User’s Manual S19262EJ3V0UM
10
CHAPTER 1 OVERVIEW
This chapter describes the Universal Asynchronous Receiver/Transmitter (UART) for EM1.
1.1 Function
Overview
The UART block incorporated in EM1 has two 64-byte FIFO buffers, one for transmission and one for reception,
and is compatible with TL16C750, a general-purpose UART chip.
The IrDA SIR encoder/decoder is provided for the serial interface, which enables transmission and reception by
using the RZI (Return-to-Zero-Inverted) signal.
1.2 Features
Three UART blocks: UART0, UART1, and UART2
Two 64-byte FIFO buffers, one for transmission and one for reception
The following operating modes are available:
Non-FIFO mode (16450 mode)
16-byte FIFO mode (16550 mode)
64-byte
FIFO
mode
Programmable auto-RTS and auto-CTS
Standard asynchronous communication control bits (start, stop, and parity bits) can be added to or deleted from
transmitted and received serial data. The following items can be specified:
Character length: 5, 6, 7 or 8 bits
Parity bit:
Even parity, odd parity, or no parity bit
Stop bit:
1 or 2 bits
Baud rate:
Reference clock frequency division ratio selectable from 1 to (2
16
1)
Modem control interface (CTS, RTS, DSR, DTR, RI, DCD)
IrDA SIR encoder/decoder (2.4 to 115.2 kbps)
1.3 I/O
Signals
The following signals are used for UART communication.
UARTx_SIN: UARTx data input (external pins)
UARTx_SOUT: UARTx data output (external pins)
UARTx_CTSB: UARTx transmission enable input (low active) (external pins)
UARTx_RTSB: UARTx transmission request output (low active) (external pins)
XIN: Operating clock input from ASMU (U7x_SCLK) (internal clock input)
MR: Master reset input from ASMU (U7x_RSTZ) (internal reset input)
Remark
x = 0 to 2
