CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
36
3.3.5 IR control register 4
This register (IRCR4: 5000_0050H (UART0), 5001_0050H (UART1), 5002_0050H (UART2)) specifies the receive
data mask period to add at the end of IR transmission.
The IRCR2, IRCR3, and IRCR4 register bits (MASK_PERIOD[19:0], 20 bits in total) are used for specification.
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Reserved MASK_PERIOD[19:16]
Name R/W
Bit
After
Reset
Function
Reserved
R
15:4
0
Reserved. When these bits are read, 0 is returned for each bit.
MASK_PERIOD[19:16]
R/W
3:0
00H
Specifies the receive data mask period to add at the end of IR
transmission. The higher 4 bits are specified.
Caution The mask extension period is expressed by using the following equation:
Mask extension period [
s) = (MASK_PERIOD[19:0] + 2)
1/f
XIN
(MHz)
Bit time
UARTx_SOUT
(IR_TXPSEL = 0)
Receive data
masking
Start
0
1
0
1
0
0
1
1
0
1
Stop
Mask extension
period
Transmit data
