CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
32
3.2.14 Hardware status register 3
This additional register (HCR3: 5000_0034H (UART0), 5001_0034H (UART1), 5002_0034H (UART2)) is used to
check the transmit FIFO status.
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
Transmitter
FIFO Overrun
Transmitter FIFO Data Count[6:0]
Name R/W
Bit
After
Reset
Function
Reserved
R
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
Transmitter FIFO Overrun
R
7
0
When data is written to the transmit FIFO when it is full or when 2-
byte data is written to the transmit FIFO when only 1 free byte space
is available, an overrun error occurs and this bit is set to 1.
Reading this register clears this bit to “0”.
Caution If an overrun error occurs, the transmit FIFO is no
longer written. No interrupt request is caused by an
overrun error.
Transmitter FIFO Data
Count[6:0]
R
6:0
0
Indicates the number of data items remaining in the transmit FIFO.
