CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
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Table 3-2. Interrupt Indication and Prioritization of Interrupt Sources (Bits 3 to 0 of IIR)
IIR[3:0]
Priority
Interrupt Type
Interrupt Source
Interrupt Reset Method
0001 (1h)
None
None
None
None
0110 (6h)
1
Reception error
(receiver line status)
When at least one of the following
occurs:
Overrun
Parity error
Framing error
Break interrupt
When the line status register
(LSR) is read
0100 (4h)
2
Reception completion
(received data available)
In non-FIFO mode
When data reception in the receive
buffer register is completed
In FIFO mode
When the amount of data in the
receive FIFO exceeds the trigger
level
In non-FIFO mode
When the receive buffer
register (RBR) is read
In FIFO mode
When the receive FIFO is
read and the amount of data
in the receive FIFO becomes
less than the trigger level
1100 (Ch)
Timeout
When data reception timed out while
the receive FIFO was used
When the receive FIFO is
read
0010 (2h)
3
Transmit buffer empty
(transmit hold register (THR)
empty)
Transmit hold register (THR) or
transmit FIFO is empty
When the IIR register is read
or data is written in the
transmit hold register (THR)
or transmit FIFO
0000 (0h)
4
Modem status
When at least one of the following
occurs:
CTS
DSR (internal signal)
DCD (internal signal)
Trailing edge RI (internal signal)
When the modem status
register (MSR) is read
Caution A transmit buffer empty interrupt (bits 3 to 0 of IIR register = 0010) is canceled by reading the IIR
register or writing data to the transmit hold register (THR) or transmit FIFO. Specifically, the
following operation is performed for reading the IIR register.
If the transmit buffer is empty when the IIR register is read to check the interrupt source, the read
operation masks the transmit buffer empty interrupt and this interrupt no longer occurs. This
masking is canceled when data is written to the transmit buffer, and the subsequent transmit
buffer empty interrupts are output.
