CHAPTER 3 REGISTERS
User’s Manual S19262EJ3V0UM
34
3.3.2 IR control register 1
This register (IRCR1: 5000_0044H (UART0), 5001_0044H (UART1), 5002_0044H (UART2)) specifies the valid
reception pulse width.
15 14 13 12 11 10 9 8
Reserved
7 6 5 4 3 2 1 0
PULSE_WIDTH[7:0]
Name R/W
Bit
After
Reset
Function
Reserved
R
15:8
0
Reserved. When these bits are read, 0 is returned for each bit.
PULSE_WIDTH[7:0]
R/W
7:0
02H
Specifies the valid reception pulse width.
Valid width: “Value set to this bit + 1” × 1 / f
XIN
or longer
Settable range: 02H to FFH (The settings 00H and 01H are
prohibited.)
Cautions 1. The valid reception pulse width is expressed by using the following expression:
Valid reception pulse width (
s)
(PULSE_WIDTH[7:0] + 1)
1/f
XIN
(MHz)
2. Valid reception pulses are detected by sampling reception pulses based on the XIN clock
cycles. When the pulse level (specified by the IR_RXPSEL bit of the IRCR0 register) is
successively detected the number of times specified for this register, the pulse is modulated
as a valid pulse.
Depending on the phase of the reception pulse and XIN clock, a pulse that does not satisfy
the above expression might be modulated as a valid pulse. The following shows the
condition under which the reception pulse is always judged to be invalid:
Invalid reception pulse width (
s) < Approx. (PULSE_WIDTH[7:0]
1)
1/f
XIN
(MHz)
Example
When the PULSE_WIDTH field is set to 02H
<1> Valid reception pulse width (
s)
3
1/f
XIN
(MHz)
<2> Invalid reception pulse width (
s) < 1
1/f
XIN
(MHz)
Reception pulse
<1>
<2>
XIN
