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CHAPTER 3 REGISTERS

User’s Manual S19262EJ3V0UM

3.2.12 Hardware control register

This additional register (HCR0: 5000_002CH (UART0), 5001_002CH (UART1), 5002_002CH (UART2)) controls

the DMA controller and other hardware.

15 14 13 12 11 10 9 8

Reserved

7 6 5 4 3 2 1 0

SW Reset

RTS Mode

DMA 2Byte

Access Enable

Receiver

timeout DMA

Disable

Receiver DMA

Mode

Transmitter

DMA Mode

Receiver DMA

Enable

Transmitter

DMA Enable

Name R/W

Bit

After

Reset

Function

Reserved

15:8

Reserved. When these bits are read, 0 is returned for each bit.

SW Reset

R/W

Setting this bit to 1 resets internal UART registers, except for

registers for the transmit and receive FIFOs and baud rate generator

(RBR/THR, DLL, and DLM). Setting this bit to 0 cancels the reset.

Caution Before executing a software reset, reset the transmit

and receive FIFOs (bits 2 and 1 of FCR register). After

that, registers other than the DLL and DLM registers

must be set up again.

RTS Mode

R/W

Selects the RTS mode when auto-RTS is used.

0: Auto-RTS mode 0

1: Auto-RTS mode 1

DMA 2Byte Access

Enable

R/W

Selects the width of data to transfer to the transmit and receive

FIFOs via DMA.

0: 1 byte

1: 2 bytes

This setting affects the conditions for generating DMA request

signals.

Receiver timeout DMA

Disable

R/W

Specifies whether to include the timeout event in the reception DMA

transfer request sources.

0: Includes the timeout event in the reception DMA transfer request

sources.

1: Excludes the timeout event from the reception DMA transfer

request sources (and automatically adds it to the interrupt

sources).

Receiver DMA Mode

R/W

Transmitter DMA Mode

R/W 2

Specifies the DMA request mode separately for transmission and

reception. These bits are used with bit 3 of the FCR register.

Receiver DMA Enable

R/W

Specifies whether to enable the reception DMA request output.

0: Disables reception DMA requests.

1: Enables reception DMA requests.

Transmitter DMA

Enable

R/W

Specifies whether to enable the transmission DMA request output.

0: Disables transmission DMA requests.

1: Enables transmission DMA requests.

Summary of Contents for EMMA Mobile 1

Page 1: ...ok over all the business of both companies Therefore although the old company name remains in this document it is a valid Renesas Electronics document We appreciate your understanding Renesas Electron...

Page 2: ...t for an application categorized as Specific or for which the product is not intended where you have failed to obtain the prior written consent of Renesas Electronics The quality grade of each Renesas...

Page 3: ...Multimedia Processor for Mobile Applications UART Interface User s Manual EMMA MobileTM 1 Printed in Japan Document No S19262EJ3V0UM00 3rd edition Date Published September 2009 2009...

Page 4: ...User s Manual S19262EJ3V0UM 2 MEMO...

Page 5: ...including work benches and floors should be grounded The operator should be grounded using a wrist strap Semiconductor devices must not be touched with bare hands Similar precautions need to be taken...

Page 6: ...en measures to prevent radioactive rays in the product design When customers use NEC Electronics products with their products customers shall on their own responsibility incorporate sufficient safety...

Page 7: ...ion of functions Chapter 5 Usage How to Read This Manual It is assumed that the readers of this manual have general knowledge of electricity logic circuits and microcontrollers To understand the funct...

Page 8: ...E ITU R BT 656 Interface S19257E LCD Controller S19258E MICROWIRE S19259E NAND Flash Interface S19260E SPI S19261E UART Interface This manual Image Composer S19263E Image Processor Unit S19264E System...

Page 9: ...10 Divisor latch LS byte register 28 3 2 11 Divisor latch MS byte register 29 3 2 12 Hardware control register 30 3 2 13 Hardware status register 2 31 3 2 14 Hardware status register 3 32 3 3 IR Encod...

Page 10: ...IR encoder 42 4 6 2 Reception data demodulation by IR decoder 42 4 6 3 Masking of reception data for IR decoder echo cancellation 43 4 6 4 Cautions on using IR encoder decoder 44 CHAPTER 5 USAGE 45 5...

Page 11: ...ion normal operation is not guaranteed In this case initialize the register 19 Table 3 3 Reception Trigger Level Settings Bits 7 and 6 of FCR 19 Table 3 4 DMA Mode Settings Bit 3 of FCR and Bits 3 and...

Page 12: ...ammable auto RTS and auto CTS Standard asynchronous communication control bits start stop and parity bits can be added to or deleted from transmitted and received serial data The following items can b...

Page 13: ...device data GIO_P85 URT1_SRIN URT0_RTSB Output 0 Prepared to transmit or receive data GIO_P86 URT1_SOUT URT1_SRIN Input Serial data GIO_P85 URT0_CTSB URT1_RTSB Output 0 Serial data GIO_P86 URT0_RTSB U...

Page 14: ...er LCR R W 0000H 0014H Modem control register MCR R W 0000H 0018H Line status register LSR R 0060H 001CH Modem status register MSR R 00xxHNote 1 0020H Scratch register SCR R W 0000H 0024H Divisor latc...

Page 15: ...r is stored as data to transmit Data of the lowest bit D0 is transmitted or received first Only the lower bytes D 7 0 are used This register can be accessed in byte units via the host bus interface If...

Page 16: ...y 1 byte of data is stored an underrun error occurs and data is not read from the receive FIFO All zeros are output to the host bus interface When an underrun error occurs bit 7 of the HCR2 register i...

Page 17: ...y transmit hold register THR empty interrupt 0 Disables the transmit buffer empty interrupt 1 Enables the transmit buffer empty interrupt ERBI R W 0 0 Specifies whether to enable the reception complet...

Page 18: ...ction Reserved R 15 8 0 Reserved When these bits are read 0 is returned for each bit FIFOs Enabled 1 0 R 7 6 00b Indicates the FIFO operating mode 00b Non FIFO mode 16450 mode 11b 16 byte 64 byte FIFO...

Page 19: ...on timed out while the receive FIFO was used When the receive FIFO is read 0010 2h 3 Transmit buffer empty transmit hold register THR empty Transmit hold register THR or transmit FIFO is empty When th...

Page 20: ...s the FIFO capacity 0 16 bytes 16550 mode 1 64 bytes Reserved R W 4 0 Reserved Written data is ignored DMA Mode Select R W 3 0 Specifies the DMA mode in FIFO mode The DMA mode is specified by setting...

Page 21: ...n the DMA access data width is one byte bit 5 of HCR0 0 Mode 0 The receive FIFO stores 1 or more bytes of data The receive FIFO is empty Receive DMA request Mode 1 The amount of data in the receive FI...

Page 22: ...g in the receive FIFO becomes 1 byte When receiving an odd number of data bytes use 1 byte access or notify the timeout event by using an interrupt bit 4 of HCR0 register 1 and read the timeout data b...

Page 23: ...l R W 6 0 Controls break state generation and transmission The serial output UARTx_SOUT is forcibly set to 0 while this bit is set to 1 and such output is canceled when this bit is set to 0 This bit d...

Page 24: ...erred via serial transmission and reception 00 5 bits 01 6 bits 10 7 bits 11 8 bits If a register value is changed during operation normal operation is not guaranteed In this case initialize the regis...

Page 25: ...Reserved R W 4 0 Reserved OUT2 R W 3 0 Selects the level of the general purpose output OUT2Z internal signal 0 High inactive 1 Low active In local loopback mode this bit controls DCDZ internal signal...

Page 26: ...e stopped When the data in the receive FIFO is read and the FIFO empties the pin is pulled low requesting transmission Auto RTS mode 1 In the 16 byte FIFO mode the RTSZ pin is pulled high when the amo...

Page 27: ...transmit buffer or transmit shift register THRE R 5 1 This bit is set to 1 when the transmit buffer THR register or transmit FIFO empties This bit is cleared to 0 when at least 1 byte of data is writ...

Page 28: ...parity error is detected when the data is read OE R 1 0 This bit is set to 1 when a receive overrun error is detected Reading this register clears this bit to 0 A receive overrun occurs when the rece...

Page 29: ...nput 0 High inactive 1 Low active In local loopback mode the value set to bit 0 DTR internal signal of the MCR register is read CTS R 4 Undefined Indicates the inverted level of UARTx_CTSB pin input 0...

Page 30: ...rator Set up this register in combination with the DLM register that specifies the higher 8 bits The baud rate generator divides the reference clock XIN and generates a 16x baud rate clock for the tra...

Page 31: ...ceive blocks by using the value specified in this register 15 14 13 12 11 10 9 8 Reserved 7 6 5 4 3 2 1 0 Divisor 15 8 Name R W Bit After Reset Function Reserved R 15 8 0 Reserved When these bits are...

Page 32: ...de R W 6 0 Selects the RTS mode when auto RTS is used 0 Auto RTS mode 0 1 Auto RTS mode 1 DMA 2Byte Access Enable R W 5 0 Selects the width of data to transfer to the transmit and receive FIFOs via DM...

Page 33: ...are read 0 is returned for each bit Receiver FIFO Underrun R 7 0 When data is read from the receive FIFO when it is empty or when reading of 2 byte data from the receive FIFO is attempted when only 1...

Page 34: ...eserved When these bits are read 0 is returned for each bit Transmitter FIFO Overrun R 7 0 When data is written to the transmit FIFO when it is full or when 2 byte data is written to the transmit FIFO...

Page 35: ...turned for each bit Reserved R W 7 0 Reserved Written data is ignored IR_MASK_OFF R W 6 0 Specifies whether to enable masking of received data stopping pulse detection for echo cancellation 0 Enables...

Page 36: ...ng expression Valid reception pulse width s PULSE_WIDTH 7 0 1 1 fXIN MHz 2 Valid reception pulses are detected by sampling reception pulses based on the XIN clock cycles When the pulse level specified...

Page 37: ...7 0 R W 7 0 00H Specifies the receive data mask period to add at the end of IR transmission The lower 8 bits are specified 3 3 4 IR control register 3 This register IRCR3 5000_004CH UART0 5001_004CH...

Page 38: ...erved 7 6 5 4 3 2 1 0 Reserved MASK_PERIOD 19 16 Name R W Bit After Reset Function Reserved R 15 4 0 Reserved When these bits are read 0 is returned for each bit MASK_PERIOD 19 16 R W 3 0 00H Specifie...

Page 39: ...t be reset by using bit 1 of the FCR register to clear error information in the FIFO 3 Interrupt signal INTRPT After the INTRPT signal related to data transfer is pulled high it stays at high level un...

Page 40: ...0 DR of the LSR register is set to 1 When the receive FIFO empties the DR bit is cleared 4 2 2 Operation in FIFO polled mode When the FIFO is enabled bit 0 of the FCR register 1 bits 3 to 0 of the IE...

Page 41: ...empty transmit hold register THR empty interrupt Bit 1 ETBEI of the IER register Reception error received data available timeout interrupt Bit 0 ERBI of the IER register 4 4 Clock and Reset The follow...

Page 42: ...CHAPTER 4 DESCRIPTION OF FUNCTIONS User s Manual S19262EJ3V0UM 40 4 5 2 Timing of auto flow CTS control 4 5 3 Timing of auto flow RTS control...

Page 43: ...ata path used for transmission and reception via the UARTx_SIN and UARTx_SOUT pins Figure 4 1 IR Encoder Decoder Block Diagram Receive shift register RSR Sel 0 XIN RZI to NRZ converter Receive pulse d...

Page 44: ...valid value set to the PULSE_WIDTH 7 0 bits of IRCR1 register or longer otherwise it outputs 1 The polarity of reception pulses can be selected by using bit 5 IR_RXPSEL of the IRCR0 register Figure 4...

Page 45: ...red valid reception pulse width s 3 Remark fXIN Frequency of reference clock XIN 4 6 3 Masking of reception data for IR decoder echo cancellation The IR decoder can mask reception data stop pulse dete...

Page 46: ...s The interface protocol prescribed by IrDA concerns the infrared IR interface and the electrical interface 1 and 2 in Figure 4 4 is not prescribed When using the IR encoder decoder thoroughly evaluat...

Page 47: ...of the LCR register Specify the number of stop bits by using bit 2 of the LCR register Select no parity even parity odd parity or stick parity by using bits 5 to 3 of the LCR register 4 Modem interfa...

Page 48: ...Frequency Hz Clock Source Baud Rate bps Error Range DLMR DLLR Actual Baud Rate bps Error 7 168 M PLL3 32 2400 4 0 187 2395 72193 0 178253 4800 0 93 4817 2043 0 3584229 9600 0 47 9531 91489 0 70922 19...

Page 49: ...ual S19262EJ3V0UM 47 Revision History Date Revision Comments February 10 2009 1 0 April 27 2009 2 0 Incremental update from comments to the 1 0 September 30 2009 3 0 Incremental update from comments t...

Page 50: ...02 8175 9600 http www tw necel com NEC Electronics Singapore Pte Ltd 238A Thomson Road 12 08 Novena Square Singapore 307684 Tel 6253 8311 http www sg necel com NEC Electronics Korea Ltd 11F Samik Lav...

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