RTL8169
2002/03/27
Rev.1.21
17
6.4 Command
(Offset 0037h, R/W)
Bit
R/W
Symbol
Description
7:5 -
-
Reserved
4 R/W RST
Reset:
Setting this bit to 1 forces the RTL8169 into a software reset
state which disables the transmitter and receiver, reinitializes the FIFOs,
and resets the system buffer pointer to the initial value (the start address
of each descriptor group set in TNPDS, THPDS and RDSAR registers).
The values of IDR0-5, MAR0-7 and PCI configuration space will have
no changes. This bit is 1 during the reset operation, and is cleared to 0
by the RTL8169 when the reset operation is complete.
3 R/W RE
Receiver Enable
2 R/W TE
Transmit Enable
1:0 -
-
Reserved
6.5 TPPoll: Transmit Priority Polling
(Offset 0038h, R/W)
Bit
R/W
Symbol
Description
7 W
HPQ
High Priority Queue polling:
Writing a ‘1’ to this bit will notify the
RTL8169 that there is a high priority packet(s) waiting to be
transmitted. The RTL8169 will clear this bit automatically after all
high priority packets have been transmitted.
Writing a ‘0’ to this bit has no effect.
6 W
NPQ
Normal Priority Queue polling:
Writing a ‘1’ to this bit will notify
the RTL8169 that there is a normal priority packet(s) waiting to be
transmitted. The RTL8169 will clear this bit automatically after all
normal priority packets have been transmitted.
Writing a ‘0’ to this bit has no effect.
5:1 -
-
Reserved
0 W
FSWInt
Forced Software Interrupt:
Writing a ‘1’ to this bit will trigger an
interrupt, and the SWInt bit (bit8, ISR, offset3Eh-3Fh) will set.
The RTL8169 will clear this bit automatically after the SWInt bit (bit8,
ISR) is cleared.
Writing a ‘0’ to this bit has no effect.
