RTL8169
2002/03/27
Rev.1.21
28
6.17 Multiple Interrupt Select
(Offset 005Ch-005Dh, R/W)
Bit
R/W
Symbol
Description
15:12 -
-
Reserved
11:0 R/W MISR11-0
Multiple Interrupt Select:
Indicates that the RTL8169 will make a
receive interrupt after the RTL8169 has transferred the data bytes
specified in this register into the system memory. If the value of this
register is zero, there will be no early receive interrupts before the whole
received packet is transferred to system memory. Bit1, 0 must be zero.
When MulERINT=1, any received packet invokes an early interrupt according to the MISR[11:0] setting in early mode.
6.18 PHYAR: PHY Access
(Offset 0060h-0063h, R/W)
PHY address is fixed at 00001.
Bit
R/W
Symbol
Description
31 R/W
Flag
Flag bit, used as PCI VPD access method:
1: Write data to MII register, and turn to 0 automatically whenever
the RTL8169 has completed writing to the specified MII register.
0: Read data from MII register, and turn to 1 automatically whenever
the RTL8169 has completed retrieving data from the specified MII
register.
30:21 -
-
Reserved
20:16 R/W
RegAddr4-0
5-bit GMII/MII register address.
15:0 R/W
Data15-0
16-bit GMII/MII register data.
6.19 TBICSR: Ten Bit Interface Control and Status
(Offset 0064h-0067h, R/W)
Bit
R/W
Symbol
Description
31 R/W
ResetTBI
Reset TBI:
This bit,
when set, indicates to the TBI to reset the
interfacing PHY device. This bit is cleared when the reset process is
completed.
30 R/W TBILoopBack
TBI Loopback Enable:
This bit,
when set, indicates to the TBI that
the interfacing PHY device is in loopback mode.
29 R/W
TBINWEn
TBI Auto-negotiation Enable:
This bit,
when set, enables the
auto-negotiation function for the TBI interface.
28 R/W
TBIReNW
TBI Restart Auto-negotiation:
This bit,
when set, restarts the
auto-negotiation. This bit is cleared when the auto-negotiation
completes.
27:26 -
-
Reserved
25 R
TBILinkOk
TBI Link Ok:
This bit,
when set, indicates that the channel
connecting to the link partner is established.
24 R TBINWComplete
TBI Nway Complete:
This bit,
when set, indicates that the
auto-negotiation process has completed in TBI mode.
23:20
TXOSETST3-0
Reserved:
For Realtek internal testing.
19 -
-
Reserved
18:16
ANST2-0
Reserved:
For Realtek internal testing.
15:13 -
-
Reserved
12:8
RXST4-0
Reserved:
For Realtek internal testing.
7:4
SYNCST3-0
Reserved:
For Realtek internal testing.
3:0
TXCGST3-0
Reserved:
For Realtek internal testing.