RTL8169
2002/03/27
Rev.1.21
31
6.24 C+CR: C+ Command
(Offset 00E0h-00E1h, R/W)
Bit
R/W
Symbol
Description
15:10 -
-
Reserved
9 R/W
ENDIAN
Endian Mode:
1: Big-endian mode.
0: Little-endian mode.
8 -
-
Reserved
(Home LAN Enable, always 0)
7 -
-
Reserved
6 R/W
RxVLAN
Receive VLAN De-tagging Enable:
1: Enable; 0: Disable.
5 R/W
RxChkSum
Receive Checksum Offload Enable:
1: Enable; 0: Disable.
4 R/W
DAC
PCI Dual Address Cycle Enable:
When set, the RTL8169 will
perform Tx/Rx DMA using PCI Dual Address Cycle only when the
High 32-bit buffer address is not equal to 0.
1: Enable; 0: Disable (initial value at power-up).
3 R/W
MulRW
PCI Multiple Read/Write Enable:
If this bit is enabled, the setting of
Max Tx/Rx DMA burst size is no longer valid.
1: Enable; 0: Disable.
2:0 -
-
Reserved
This register is the key before configuring other registers and descriptors.
This register is word access only, byte access to this register has no effect.
6.25 RDSAR: Receive Descriptor Start Address
(Offset 00E4h-00EBh, R/W)
Bit
R/W
Symbol
Description
63:0 R/W
RDSA
Receive Descriptor Start Address
: 64-bit address, 256-byte
alignment address.
Bit[31:0]: Offset E7h-E4h, low 32-bit address.
Bit[63:32]: Offset EBh-E8h, high 32-bit address.
6.26 ETThR: Early Transmit Threshold
(Offset 00ECh, R/W)
Bit
R/W
Symbol
Description
7:6 -
-
Reserved
5:0 R/W
ETTh
Early Tx Threshold:
Specifies the threshold level in the Tx FIFO to
begin the transmission. When the byte count of the data in the Tx
FIFO reaches this level, (or the FIFO contains at least one complete
packet) the RTL8169 will transmit the packet.
-
These fields count from 000001 to 111111 in units of 32 bytes.
-
This threshold must be avoided from exceeding 2K bytes.
-
000000 is reserved. Do not set to this value.
