Realtek RTL8169 Manual Download

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RTL8169

2002/03/27

Rev.1.21

Asymmetric Pause:

When this bit is set, the value of bit7 (Pause)

indicates the direction that PAUSE frames are supported by the link partner.

PS1 PS2

Capability

0 0

Pause.

Asymmetric PAUSE toward link
partner.

1 0

Symmetric

PAUSE.

Both symmetric PAUSE and
asymmetric PAUSE toward local
device.

8:7 R PS2(ASM_DIR),

PS1(PAUSE)

6 R

HalfDup

Half Duplex:

When set, the link partner supports half duplex.

5 R

FullDup

Full Duplex:

When set, the link partner supports full duplex.

4:0 -

Reserved

6.22 PHYStatus: PHY(GMII or TBI) Status
(Offset 006Ch, R)

Bit

R/W

Symbol

Description

7 R

EnTBI

TBI Enable:

This bit is autoloaded from the EEPROM.

1: TBI mode, 0: GMII(MII) mode.

6 R

TxFlow

Transmit Flow Control:

1: Enabled, 0: Disabled.

5 R

RxFlow

Receive Flow Control:

1: Enabled, 0: Disabled.

1000MF

Link speed is 1000Mbps and in full-duplex. (GMII mode only)

100M

Link speed is 100Mbps. (GMII or MII mode only)

10M

Link speed is 10Mbps. (GMII or MII mode only)

LinkSts

Link Status. 1: Link Ok, 0: No Link.

0 R

FullDup

Full-Duplex Status:

1: Full-duplex mode, 0: Half-duplex mode.

MII registers polling cycle: 320ns * (32 MDC clock + 32 MDC clock) * 6 registers

6.23 RMS: Receive (Rx) Packet Maximum Size
(Offset 00DAh-00DBh, R)

Bit

R/W

Symbol

Description

15:14 -

Reserved

13:0 R/W

RMS

Rx packet Maximum Size:

i. This register should be always set to a value other than 0, in

order to receive packets.

ii.

The maximum size supported is 2

-1, i.e., 16K-1 bytes.

Summary of Contents for RTL8169

Page 1: ...face 36 8 1 1 Byte Ordering 36 8 1 2 Interrupt Control 36 8 1 3 Latency Timer 36 8 1 4 64 Bit Data Operation 37 8 1 5 64 Bit Addressing 37 8 2 Bus Operation 37 8 2 1 Target Read 37 8 2 2 Target Write...

Page 2: ...the internal clock source or 125MHz clock provided from external PHYceiver Compliant to PC97 PC98 PC99 and PC2001 standards Supports Wake On LAN function and remote wake up Magic Packet LinkChg and Mi...

Page 3: ...ty The PCI specification is inherently little endian The RTL8169 contains the ability to do little endian to big endian swaps It is also possible that the RTL8169 can be used as a basis for a RISC CPU...

Page 4: ...Logic FIFO Transmit Receive Logic Interface Early Interrupt Control Logic FIFO Control Logic Packet Type Discriminator Power Control Logic PCI Interface Register Packet Length Register Early Interrup...

Page 5: ...MD2 124 MD3 123 MD4 122 MD5 121 MD6 120 VDD18 119 MD7 118 LED0 117 GND 116 LED1 115 LED2 114 LED3 113 VDD33 112 MA16 111 MA15 110 MA14 109 MA13 108 NC 107 MA12 106 NC 105 MA11 102 MA9 101 MA8 100 MA7...

Page 6: ...CardB_En 0 bit2 Config3 This signal is used to inform the motherboard to execute the wake up process The motherboard must support Wake On LAN WOL There are 4 choices of output including active high ac...

Page 7: ...n address phase when using DAC commands or when REQ64B is asserted the actual bus command is transferred on C BE7 4 otherwise these bits are reserved and indeterminate During a data phase C BE7 4 are...

Page 8: ...ansaction takes place at the rising edge of CLK when both IRDYB and TRDYB are asserted low As a target this signal indicates that the master has put data on the bus TRDYB S T S 205 Target Ready This i...

Page 9: ...O I 112 109 107 105 104 102 100 97 95 101 99 Boot PROM Address Bus These pins are used to access up to a 128k byte flash memory or EPROM MA16 3 Output pins to the Boot PROM address bus MA8 Input pin a...

Page 10: ...nd it used as the 125MHz transmit clock to an external PMD and is the reference for transmit TBI signaling TxCLK I 147 Transmit Clock MII mode only TxCLK is a continuous clock that provides a timing r...

Page 11: ...he frame being received The RxER may be asserted for one or more clock cycles Rx 9 In TBI mode Rx 9 is the MSB of the 10 bit vector representing one receive code group Rx 0 is the first bit received a...

Page 12: ...0 Management Data Input Output Bi directional signal used to transfer or receive control and status information from the PHY device MDIO is driven and sampled synchronously with respect to MDC In TBI...

Page 13: ...ved 0020h 0027h R W TNPDS Transmit Normal Priority Descriptors Start address 64 bit 256 byte alignment 0028h 002Fh R W THPDS Transmit High Priority Descriptors Start address 64 bit 256 byte alignment...

Page 14: ...2 128bit low D Word 009Ch 00A3h R W Wakeup2HD Power Management wakeup frame2 high D Word 00A4h 00ABh R W Wakeup3LD Power Management wakeup frame3 128bit low D Word 00ACh 00B3h R W Wakeup3HD Power Mana...

Page 15: ...bit counter of Frame Alignment Error packets MII mode only 32 Tx1Col 32 bit counter of those Tx Ok packets with only 1 collision happened before Tx Ok 36 TxMCol 32 bit counter of those Tx Ok packets w...

Page 16: ...pins 6 3 ERSR Early Rx Status Offset 0036h R Bit R W Symbol Description 7 4 Reserved 3 R ERGood Early Rx Good packet This bit is set whenever a packet is completely received and the packet is good Wri...

Page 17: ...0038h R W Bit R W Symbol Description 7 W HPQ High Priority Queue polling Writing a 1 to this bit will notify the RTL8169 that there is a high priority packet s waiting to be transmitted The RTL8169 wi...

Page 18: ...available Interrupt 1 Enable 0 Disable 6 R W FOVW Rx FIFO Overflow Interrupt 1 Enable 0 Disable 5 R W PUN LinkChg Packet Underrun Link Change Interrupt 1 Enable 0 Disable 4 R W RDU Rx Buffer Overflow...

Page 19: ...Rx Descriptor Unavailable When set to 1 this bit indicates that the Rx descriptor is unavailable The MPC Missed Packet Counter offset 4Ch 4Fh indicates the number of packets discarded after Rx FIFO o...

Page 20: ...IFG 100MHz ns IFG 10MHz s 0 1 1 96 960 9 6 1 0 1 96 8 960 8 10 9 6 8 0 1 1 1 1 96 16 960 16 10 9 6 16 0 1 0 0 1 96 24 960 24 10 9 6 24 0 1 0 1 0 96 48 960 48 10 9 6 48 0 1 25 24 R W IFG1 0 Other valu...

Page 21: ...larger than 8 bytes When this bit is cleared the RTL8169 only calculates the CRC of any received packet with a length larger than 64 bytes The power on default is zero If AER or AR is set the RTL8169...

Page 22: ...ccept Error Packet When set to 1 all packets with CRC error alignment error and or collided fragments will be accepted When set to 0 all packets with CRC error alignment error and or collided fragment...

Page 23: ...ons are disabled The 93C46 93C56 can be directly accessed via bit3 0 which now reflect the states of EECS EESK EEDI EEDO pins respectively 1 1 Config register write enable Before writing to CONFIGx re...

Page 24: ...in is an active high signal LWACT LWAKE output 0 1 0 Active high Active low LWPTN 1 Positive pulse Negative pulse 4 R W LWACT Default value 3 R MEMMAP Memory Mapping The operational registers are mapp...

Page 25: ...ddressed to the node for a specific data sequence which indicates to the controller that this is a Magic Packet frame A Magic Packet frame must also meet the basic requirements Destination address Sou...

Page 26: ...le CardBus only 1 Enable the 4 Function Registers Function Event Register Function Event Mask Register Function Present State Register and Function Force Event Register for CardBus application 0 Disab...

Page 27: ...ticast address 0 Default value Disable Multicast Wakeup Frame with mask bytes of only DID field which is a multicast address The power on default value of this bit is 0 4 R W UWF Unicast Wakeup Frame...

Page 28: ...I MII register address 15 0 R W Data15 0 16 bit GMII MII register data 6 19 TBICSR Ten Bit Interface Control and Status Offset 0064h 0067h R W Bit R W Symbol Description 31 R W ResetTBI Reset TBI This...

Page 29: ...c PAUSE toward local device 8 7 R W PS2 ASM_DIR PS1 PAUSE 6 Reserved 5 R FullDup Full Duplex This bit is always set Full duplex capability is advertised toward the link partner in NWay mode 4 0 Reserv...

Page 30: ...This bit is autoloaded from the EEPROM 1 TBI mode 0 GMII MII mode 6 R TxFlow Transmit Flow Control 1 Enabled 0 Disabled 5 R RxFlow Receive Flow Control 1 Enabled 0 Disabled 4 R 1000MF Link speed is 10...

Page 31: ...is register is the key before configuring other registers and descriptors This register is word access only byte access to this register has no effect 6 25 RDSAR Receive Descriptor Start Address Offse...

Page 32: ...Mask Offset 00F4h 00F7h R W Bit R W Symbol Description 31 16 Reserved 15 R W INTR Interrupt mask When cleared 0 setting of the INTR bit in either the Function Present State Register or the Function E...

Page 33: ...1 bit3 Config3 and FuncRegEn 1 bit1 Config3 This read only register reflects the current state of the function 6 30 Function Force Event Offset 00FCh 00FFh W Bit R W Symbol Description 31 16 Reserved...

Page 34: ...h 04h 05h DID PCI Device ID PCI configuration space offset 02h 03h 06h 07h SVID PCI Subsystem Vendor ID PCI configuration space offset 2Ch 2Dh 08h 09h SMID PCI Subsystem ID PCI configuration space off...

Page 35: ...CIS data 93C56 only 7 1 EEPROM Registers Offset Name Type Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 00h 05h IDR0 IDR5 R W 51h CONFIG0 R BS2 BS1 BS0 W 52h CONFIG1 R LEDS1 LEDS0 DVRLOAD LWACT MEMMAP IOMA...

Page 36: ...7 0 Byte 3 Byte 2 Byte 1 Byte 0 C BE 3 MSB C BE 2 C BE 1 C BE 0 LSB Little Endian Byte Ordering When configured for big endian mode ENDIAN bit 1 the byte orientation for receive and transmit data and...

Page 37: ...ress on the address bus matches the IO address range specified in IOAR for I O reads or the memory address range specified in MEM for memory reads the RTL8169 will generate DEVSELB 2 clock cycles late...

Page 38: ...ddress and FRAMEB for 1 cycle only If GNTB is asserted 3 cycles or later FRAMEB Address and Command will be generated on the clock following GNTB The device will wait for 8 cycles for the assertion of...

Page 39: ...n On the clock edge after the generation of Address and Command the data bus will become valid and the C BE bus will contain valid byte enables On the clock edge after FRAMEB was asserted IRDYB will b...

Page 40: ...queue The Tx Buffer Manager DMAs packet data from system memory and places it in the 8KB transmit FIFO and pulls data from the FIFO to send to the Tx MAC Multiple packets may be present in the FIFO al...

Page 41: ...0 IOIN W 11h R W IOAR15 IOAR14 IOAR13 IOAR12 IOAR11 IOAR10 IOAR9 IOAR8 12h R W IOAR23 IOAR22 IOAR21 IOAR20 IOAR19 IOAR18 IOAR17 IOAR16 13h R W IOAR31 IOAR30 IOAR29 IOAR28 IOAR27 IOAR26 IOAR25 IOAR24 1...

Page 42: ...ID This field will be set to a value corresponding to PCI Vendor ID in the external EEPROM If there is no EEPROM this field will default to a value of 10ECh which is Realtek Semiconductor s PCI Vendor...

Page 43: ...em Error This bit when set indicates that the RTL8169 has asserted the system error pin SERRB Writing a 1 clears this bit to 0 13 RMABT Received Master Abort This bit when set indicates that the RTL81...

Page 44: ...BASE IO Address This is set by software to the Base IO address for the operational register map 7 2 IOSIZE Size Indication Read back as 0 This allows the PCI bridge to determine that the RTL8169 requ...

Page 45: ...o the RTL8169 operational registers This register must be initialized prior to accessing any of the RTL8169 s register with memory access Bit Symbol Description 31 18 BMAR31 18 Boot ROM Base Address 1...

Page 46: ...S R W 0 0 0 0 0 0 0 0 0Dh LTR R 0 0 0 0 0 0 0 0 W LTR7 LTR6 LTR5 LTR4 LTR3 LTP2 LTR1 LTR0 0Eh HTR R 0 0 0 0 0 0 0 0 0Fh BIST R 0 0 0 0 0 0 0 0 10h IOAR R 0 0 0 0 0 0 0 1 11h R W 0 0 0 0 0 0 0 0 12h R...

Page 47: ...to a D0 state the PCI bus master mode continues to transfer the data which is not yet moved into the Tx FIFO from the last break The packet that was not transmitted completely last time is transmitte...

Page 48: ...7 of any incoming network packet The PME signal is asserted only when the following conditions are met The PMEn bit bit0 CONFIG1 is set to 1 The PME_En bit bit8 PMCSR in PCI Configuration Space is set...

Page 49: ...ata from 93C46 93C56 Reset the flag bit to 0 at the same time the VPD address is written to retrieve VPD data from EEPROM When the flag bit is set to 1 by the RTL8169 the VPD data 4 bytes per VPD acce...

Page 50: ...es Padding The RTL8169 will automatically pad any packets less than 64 bytes including 4 bytes CRC to 64 byte long including 4 byte CRC before transmitting that packet onto network medium If a packet...

Page 51: ...escriptor in descriptor ring When the NIC s internal transmit pointer reaches here the pointer will return to the first descriptor of the descriptor ring after transmitting the data relative to this d...

Page 52: ...ion and VLAN ID Please refer to IEEE 802 1Q for more VLAN tag information VIDH The high 4 bits of a 12 bit VLAN ID VIDL The low 8 bits of a 12 bit VLAN ID PRIO 3 bit 8 level priority CFI Canonical For...

Page 53: ...se LGSEN 0 0 26 19 RSVD Reserved 0 18 IPCS IP checksum offload A command bit The driver sets this bit to ask the NIC to offload the IP checksum 0 17 UDPCS UDP checksum offload A command bit The driver...

Page 54: ...criptor ring When NIC s internal transmit pointer reaches here the pointer will return to the first descriptor of the descriptor ring after transmitting the data relative to this descriptor 0 29 FS Fi...

Page 55: ...ts containing a 4 byte VLAN tag and remove the VLAN tag from the received packet If Rx VLAN Tag Removal is enabled then the 4 bytes following the source and destination addresses will be stripped out...

Page 56: ...TAVA Tag Available This bit when set indicates that the received packet is an IEEE802 1Q VLAN TAG 0x8100 available packet 4 15 0 VLAN_TAG VLAN Tag If the TAG of the packet is 0x8100 The RTL8169 MAC e...

Page 57: ...0 25 BAR Broadcast Address Received This bit when set indicates that a broadcast packet has been received BAR and MAR will not be set simultaneously 0 24 BOVF Buffer Overflow This bit when set indica...

Page 58: ...100Mbps The RTL8169 does not support half duplex mode in 1000Mbps mode Therefore there is no collision when the RTL8169 operates in 1000Mbps mode 9 4 Flow Control The RTL8169 supports IEEE802 3X flow...

Page 59: ...ad Multiple command is semantically identical to the Memory Read command except that it additionally indicates that the master may intend to fetch more than one cache line before disconnecting The mem...

Page 60: ...uration space is 8 or 16 longwords DWORDs ii The accessed address is cache line aligned iii The RTL8169 has at least 8 16 longwords DWORDs of data in its Rx FIFO iv The MWI bit 4 in the PCI Configurat...

Page 61: ...s down such as LINK10 LINK100 LINK1000 LINK10 100 1000 LINK10 ACT LINK100 ACT or LINK1000 ACT Whenever link status is established the specific link LED pin is driven low Once a cable is disconnected t...

Page 62: ...tivity is occurring Power On Transmitting Packet LED High LED High for 100 10 ms LED Low for 12 2 ms No Yes 9 6 4 Tx Rx LED In 10 100 1000Mbps mode blinking of the Tx Rx LED indicates that both transm...

Page 63: ...mode blinking of the LINK ACT LED indicates that the RTL8169 is linked and operating properly This LED high for extended periods indicates that a link problem exists Power On Link LED High LED Low LE...

Page 64: ...n both MII and GMII modes 9 7 3 Ten Bit Interface TBI The TBI provides a port for transmit and receive data for interfacing to devices that support the 1000Base X portion of the 802 3 specifications T...

Page 65: ...rface Power 3 3V Power 3 3V GMII 25MHz clock 125MHz clock LED Regulators Main Aux Power Power 3 3V 2 5V 1 8V Power 3 3V 2 5V 1 8V Power 3 3V 1 8V 10 2 1000Base X Application Optical Transceiver Extern...

Page 66: ...um Units VDD33 3 3V Supply Voltage 3 0 3 3 3 6 V VDD18 1 8V Supply Voltage 1 71 1 8 1 89 V Voh Minimum High Level Output Voltage Ioh 8mA 0 9 Vcc Vcc V Vol Maximum Low Level Output Voltage Iol 8mA 0 1...

Page 67: ...ription Minimum Typical Maximum Units TRC Read Cycle 135 ns TCE Chip Enable Access Time 200 ns TACC Address Access Time 200 ns TOES Output Enable Access Time 60 ns TCOLZ Chip Enable to Output in Low Z...

Page 68: ...tWP tDS tDH tCS tAH tDS tCOLZ tWP tCH tAH tCS tDF tCE tOOLZ tOE tOH Symbol Description Minimum Typical Maximum Units TWC Write Cycle Time 135 ns TAS Address Set up Time 0 ns TAH Address Hold Time 60 n...

Page 69: ...Symbol Parameter Min Typical Max Unit tcs Minimum CS Low Time 9346 9356 1000 250 ns twp Write Cycle Time 9346 9356 10 10 ms tsk SK Clock Cycle Time 9346 9356 4 1 us tskh SK High Time 9346 9356 1000 5...

Page 70: ...e after CLK STABLE 100 100 us T rst off Reset Active to Output Float delay 40 40 ns Trrsu REQB to REQ64B Setup Time 10 Tcyc 10 Tcyc ns Trrh RSTB to REQ64B Hold Time 0 50 0 50 ns T rhfa RSTB High to Fi...

Page 71: ...eform CLK Device 1 CLK Device 2 T_skew T_skew T_skew V_ih V_ih V_il V_il V_test V_test Clock Skew Diagram 66MHz 33MHz Symbol Parameter Min Max Min Max Units Tcyc CLK Cycle Time 15 30 30 ns Thigh CLK H...

Page 72: ...ansactions DEVSELB C BE3 0B IRDYB TRDYB AD31 0 ADDRESS CLK 1 2 3 4 5 6 7 8 9 FRAMEB 10 DATA BUS CMD BE3 0B I O Read DEVSELB C BE3 0B IRDYB TRDYB AD31 0 ADDRESS CLK 1 2 3 4 5 6 7 8 9 FRAMEB 10 DATA BUS...

Page 73: ...B C BE3 0B IRDYB TRDYB AD31 0 ADDRESS CLK 1 2 3 4 5 6 7 8 9 FRAMEB 10 DATA BUS CMD BE3 0B IDSEL Configuration Read DEVSELB C BE3 0B IRDYB TRDYB AD31 0 ADDRESS CLK 1 2 3 4 5 6 7 8 9 FRAMEB 10 DATA BUS...

Page 74: ...REQB B CLK 1 2 3 4 5 6 7 8 9 REQB A 10 BUS Arbitration DEVSELB IRDYB TRDYB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER AD31 0 ADDRESS DATA 1 DATA 2 DATA 3 CLK 1 2 3 4 5 6 7 8 9 FRAMEB C B...

Page 75: ...C BE3 0B IRDYB TRDYB AD31 0 ADDRESS DATA 1 DATA 2 DATA 3 BUS CMD BE3 0B 1 BE3 0B 2 CLK 1 2 3 4 5 6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER BE3 0B 3 Memory Write below 4GB...

Page 76: ...BE3 0B C BE7 4B IRDYB TRDYB ACK64B AD31 0 ADDRESS DATA 1 DATA 2 DATA 3 BUS CMD BE3 0B BE7 4B CLK 1 2 3 4 5 6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER Memory Read below 4GB...

Page 77: ...IRDYB TRDYB ACK64B AD31 0 ADDRESS DATA 1 DATA 2 DATA 3 BUS CMD BE3 0B 1 BE3 0B 2 CLK 1 2 3 4 5 6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER DATA 2 BE7 4B 1 BE3 0B 3 Memory...

Page 78: ...7 4B IRDYB TRDYB ACK64B AD31 0 ADDRESS BUS CMD BE3 0B BE7 4B CLK 1 2 3 4 5 6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER DATA 1 DATA 3 DATA 5 DATA 2 DATA 4 DATA 6 Memory Read...

Page 79: ...64B AD31 0 ADDRESS DATA 1 DATA 3 DATA 5 BUS CMD BE3 0B 1 BE3 0B 2 CLK 1 2 3 4 5 6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER DATA 2 BE7 4B 1 BE3 0B 3 BE7 4B 3 BE7 4B 2 DATA...

Page 80: ...0B DATA 1 DATA 2 DATA 3 HI ADDR DAC CMD Memory Read above 4GB DAC 64 bit address 32 bit data 32 bit slot DEVSELB C BE3 0B IRDYB TRDYB AD31 0 LO ADDR DATA 1 DATA 2 DATA 3 BUS CMD BE3 0B 1 BE3 0B 2 CLK...

Page 81: ...B TRDYB ACK64B AD31 0 LO ADDR CLK 1 2 3 4 5 6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER 10 BUS CMD BE3 0B BE7 4B DATA 1 DATA 2 DATA 3 HI ADDR HI ADDR DAC CMD BUS CMD Memory...

Page 82: ...AD31 0 LO ADDR DATA 1 DATA 2 DATA 3 BUS CMD BE3 0B 1 BE3 0B 2 CLK 1 2 3 4 5 6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER DATA 2 BE7 4B 1 BE3 0B 3 10 HI ADDR HI ADDR DAC CMD...

Page 83: ...K64B AD31 0 LO ADDR CLK FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER DATA 1 DATA 3 DATA 5 1 2 3 4 5 6 7 8 9 10 DATA 2 DATA 4 DATA 6 BUS CMD BE3 0B BE7 4B HI ADDR HI ADDR DAC CMD BUS...

Page 84: ...6 7 8 9 FRAMEB WAIT DATA TRANSFER WAIT WAIT DATA TRANSFER DATA TRANSFER DATA 2 BE7 4B 1 BE3 0B 3 BE7 4B 3 BE7 4B 2 DATA 6 DATA 4 10 HI ADDR HI ADDR BUS CMD DAC CMD Memory Write above 4GB DAC 64 bit a...

Page 85: ...2002 03 27 Rev 1 21 85 DEVSELB IRDYB TRDYB CLK 1 2 3 4 5 6 7 8 9 FRAMEB STOPB Target Initiated Termination Disconnect DEVSELB IRDYB TRDYB CLK 1 2 3 4 5 6 7 8 9 FRAMEB STOPB Target Initiated Terminatio...

Page 86: ...DYB CLK 1 2 3 4 5 6 7 8 9 FRAMEB FAST SUB SLOW MED NO RESPONSE ACKNOWLEDGE Master Initiated Termination Abort BUS CMD ADDRESS DATA ADDRESS DATA PERR CLK 1 2 3 4 5 6 7 8 9 FRAMEB 10 PAR PAR64 AD C BE S...

Page 87: ...0 14 26 ns tTxRV Tx Clock rise to TxD TxEN valid 20 20 ns tTxHD TxD TxEN Hold Time 5 5 ns MII Transmit Timing Parameters MII Timing MII PORT Receive RxCLK RxD 3 0 RxDV RxER Vih min Vih min Vil max Vil...

Page 88: ...max tMCC tMCH tMCL tMSU tMHT tMRV MII Management Timing Symbol Description Min Typical Max Units tMCC MDC Cycle Time 50 ns tMCH MDC High Time 25 ns tMCL MDC Low Time 25 ns tMSU MDIO Setup Time 10 ns...

Page 89: ...fRxCLK GTxCLK RxCLK frequency 125 100ppm 125 125 100ppm MHz tGCC GTxCLK RxCLK Cycle Time 7 5 8 8 5 ns tGCH GTxCLK RxCLK High Time 2 5 ns tGCL GTxCLK RxCLK Low Time 2 5 ns tR GTxCLK RxCLK Rise Time 1 n...

Page 90: ...0ppm MHz tRC Clock Rise Time of GTxCLK RxCLK0 RxCLK1 0 7 2 4 ns tFC Clock Fall Time of GTxCLK RxCLK0 RxCLK1 0 7 2 4 ns tDUTY Clock Duty Cycle of GTxCLK RxCLK0 RxCLK1 40 60 tTxSU Data Setup to of GTxCL...

Page 91: ...2 0 119 0 128 0 136 3 02 3 24 3 46 Inspection spec B 0 004 0 008 0 012 0 10 0 20 0 30 C 0 002 0 006 0 010 0 04 0 15 0 26 D 1 093 1 102 1 112 27 75 28 00 28 25 TITLE 208L QFP 28x28 mm 2 FOOTPRINT 2 6mm...

Page 92: ...2002 03 27 Rev 1 21 92 Realtek Semiconductor Corp Headquarters 1F No 2 Industry East Road IX Science based Industrial Park Hsinchu 300 Taiwan R O C Tel 886 3 5780211 Fax 886 3 5776047 WWW www realtek...

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