RTL8169
2002/03/27
Rev.1.21
2
1. Features
208 pin QFP
Supports descriptor-based buffer management
Supports Microsoft* NDIS5 Checksum Offloads (IP,
TCP, UDP), and Largesend Offload
Supports IEEE 802.1Q VLAN tagging
Supports Transmit (Tx) Priority Queue for QoS, CoS
applications
Supports major Tally Counters
10Mbps, 100Mbps, and 1000Mbps operation at
MII/GMII, and 1000Mbps at TBI interfaces
Supports 10Mbps, 100Mbps, and 1000Mbps N-way
Auto-negotiation operation
PCI local bus single-chip Fast Ethernet controller
Compliant to PCI Revision 2.2
Supports both
Little-Endian and Big-Endian
Supports 16.75MHz-66MHz PCI clock
Supports both 32-bit and 64-bit PCI bus
Supports PCI target fast back-to-back transaction
Supports Memory Read Line, Memory Read
Multiple, Memory Write and Invalidate, and
Dual Address Cycle
Provides PCI bus master data transfers and PCI
memory space or I/O space mapped data
transfers of the RTL8169 operational registers
Supports PCI VPD (Vital Product Data)
Supports ACPI, PCI power management
Supports optional PCI multi-function with
additional slave mode only functions
Supports CardBus. The CIS can be stored in 93C56 or
expansion ROM
Supports Boot ROM interface. Up to 128K bytes Boot
ROM interface for both EPROM and Flash memory
can be supported
Supports 125MHz OSC as the internal clock source or
125MHz clock provided from external PHYceiver
Compliant to PC97, PC98, PC99 and PC2001 standards
Supports Wake-On-LAN function and remote wake-up
(Magic Packet*, LinkChg and Microsoft
®
wake-up
frame)
Supports 4 Wake-On-LAN (WOL) signals (active high,
active low, positive pulse, and negative pulse)
Supports auxiliary power-on internal reset, to be ready
for remote wake-up when main power still remains off
Supports auxiliary power auto-detect, and sets the
related capability of power management registers in PCI
configuration space
Advanced power saving mode when LAN function or
wakeup function is not used
3.3V and 1.8V power supplies needed
5V tolerant I/Os
Includes a programmable, PCI burst size and early
Tx/Rx threshold
Supports a 32-bit general-purpose timer with the
external PCI clock as clock source, to generate
timer-interrupt
Contains two large independent transmit (8KB) and
receive (48KB) FIFO devices
Uses 93C46 (64*16-bit EEPROM) or 93C56
(128*16-bit EEPROM) to store resource configuration,
ID parameter, and VPD data. The 93C56 can also be
used to store the CIS data structure for CardBus
applications
Supports LED pins for various network activity
indications
Supports both digital and external analog loopback
Half/Full duplex capability (only Full duplex operation
at 1000Mbps)
Supports Full Duplex Flow Control (IEEE 802.3x)
* Third-party brands and names are the property of their
respective owners.
These specifications are subject to change without notice.
