RTL8169
2002/03/27
Rev.1.21
38
8.2.2 Target Write
A Target Write operation starts with the system generating FRAMEN, Address, and Command (0011b or 0111b). If the upper 24
bits on the address bus match IOAR (for I/O reads) or MEM (for memory reads), the RTL8169 will generate DEVSELB 2 clock
cycles later. On the 2nd cycle after the assertion of DEVSELB, the device will monitor the IRDYB signal. If IRDYB is asserted
at that time, the RTL8169 will assert TRDYB. On the next clock the 32-bit double word will be latched in, and TRDYB will be
forced HIGH for 1 cycle and then tri-stated. Target write operations must be 32-bits wide.
If FRAMEB is asserted beyond the assertion of IRDYB, the RTL8169 will still latch the first double word as described above,
but will also issue a Disconnect. That is, it will assert the STOPB signal with TRDYB. STOPB will remain asserted until
FRAMEB is detected as deasserted.
Target Write Operation
8.2.3 Master Read
A Master Read operation starts with the RTL8169 asserting REQB. If GNTB is asserted within 2 clock cycles, FRAMEB,
Address, and Command will be generated 2 clocks after REQB (Address and FRAMEB for 1 cycle only). If GNTB is asserted 3
cycles or later, FRAMEB, Address, and Command will be generated on the clock following GNTB.
The device will wait for 8 cycles for the assertion of DEVSELB. If DEVSELB is not asserted within 8 clocks, the device will
issue a master abort by asserting FRAMEB HIGH for 1 cycle, and IRDYB will be forced HIGH on the following cycle. Both
signals will become tri-state on the cycle following their deassertion.
On the clock edge after the generation of Address and Command, the address bus will become tri-state, and the C/BE bus will contain
valid byte enables. On the clock edge after FRAMEB was asserted, IRDYB will be asserted (and FRAMEB will be deasserted if this
is to be a single read operation). On the clock where both TRDYB and DEVSELB are detected as asserted, data will be latched in (and
the byte enables will change if necessary). This will continue until the cycle following the deassertion of FRAMEB.
On the clock where the second to last read cycle occurs, FRAMEB will be forced HIGH (it will be tri-stated 1 cycle later). On the
next clock edge that the device detects TRDYB asserted, it will force IRDYB HIGH. It, too, will be tri-stated 1 cycle later. This
will conclude the read operation. The RTL8169 will never force a wait state during a read operation.
