RTL8169
2002/03/27
Rev.1.21
20
6.8 Transmit Configuration
(Offset 0040h-0043h, R/W)
Bit
R/W
Symbol
Description
31 -
-
Reserved
Hardware Version ID0:
Bit30
Bit29
Bit28
Bit27
Bit26
Bit23
RTL8139 1 1 0 0 0 0
RTL8139A 1 1 1 0 0 0
RTL8139A-G
1 1 1 0 0 1
RTL8139B 1 1 1 1 0 0
RTL8130 1 1 1 1 1 0
RTL8139C 1 1 1 0 1 0
R
1 1 1 0 1 1
RTL8100 1 1 1 1 0 1
RTL8169
0
0
0
0
0
0
Reserved
All other combination
30:26 R
HWVERID0
InterFrameGap Time:
This field allows adjustment of the interframe
gap time to be longer than the standards of 9.6 µs for 10Mbps, 960 ns
for 100Mbps, and 96 ns for 1000Mbps. The time can be programmed
from 9.6 µs to 14.4 µs (10Mbps), 960ns to 1440ns (100Mbps), and 96ns
to 144ns (1000Mbps).
The setting of the inter frame gap is:
IFG[2:0] IFG@1000MHz
(ns)
IFG@100MHz
(ns)
IFG@10MHz
(µs)
0 1 1
96
960
9.6
1 0 1
96 + 8
960 + 8 * 10
9.6 + 8 * 0.1
1 1 1
96 + 16
960 + 16 * 10
9.6 + 16 * 0.1
0 0 1
96 + 24
960 + 24 * 10
9.6 + 24 * 0.1
0 1 0
96 + 48
960 + 48 * 10
9.6 + 48 * 0.1
25:24 R/W IFG1,
0
-Other values are reserved.
23 R
HWVERID1
Hardware Version ID1:
Please see HWVERID0.
22:20
-
Reserved
19 R/W IFG2
InterFrameGap2
18:17 R/W
LBK1,
LBK0
Loopback test:
There will be no packets on the (G)MII or TBI interface
in Digital loopback mode, provided the external phyceiver is also set in
loopback mode. The digital loopback function is independent of the
current link status.
For analog loopback tests, software must force the external phyceiver
into loopback mode while the RTL8169 operates normally.
00 : Normal operation
01 : Digital loopback mode
10 : Reserved
11 : Reserved
16 R/W CRC
Append CRC:
Setting this bit to 1 means that there is no CRC
appended at the end of a packet. Setting to 0 means that there is a CRC
appended at the end of a packet.
15:11 -
-
Reserved
cont...
