RTL8169
2002/03/27
Rev.1.21
21
10:8
R/W
MXDMA2, 1, 0
Max DMA Burst Size per Tx DMA Burst:
This field sets the maximum
size of transmit DMA data bursts according to the following table:
000 = 16 bytes
001 = 32 bytes
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = Unlimited
7:0 -
-
Reserved
The TCR register can only be changed after having set TE (bit2, Command register, offset 0037h).
6.9 Receive Configuration
(Offset 0044h-0047h, R/W)
Bit
R/W
Symbol
Description
31:25 -
-
Reserved
24 R/W
MulERINT
Multiple Early Interrupt Select:
When this bit is set to 1, any received
packets invoke an early interrupt according to the
MULINT<MISR[11:0]> setting in early mode.
23:17 -
-
Reserved
16
R/W
RER8
When this bit is set to 1, the RTL8169 will calculate the CRC of any
received packed with a length larger than 8 bytes.
When this bit is cleared, the RTL8169 only calculates the CRC of any
received packet with a length larger than 64-bytes. The power-on
default is zero.
If AER or AR is set, the RTL8169 always calculates the CRC of any
incoming packet with a packet length larger than 8 bytes. The RER8 is
in a “Don’t care” state in this situation.
15:13
R/W
RXFTH2, 1, 0
Rx FIFO Threshold:
Specifies the Rx FIFO Threshold level. When the
number of the received data bytes from a packet, which is being
received into the Rx FIFO of the RTL8169, has reached this level (or the
FIFO contains a complete packet), the receive PCI bus master function
will begin to transfer the data from the FIFO to the host memory. This
field sets the threshold level according to the following table:
000 = Reserved
001 = Reserved
010 = 64 bytes
011 = 128 bytes
100 = 256 bytes
101 = 512 bytes
110 = 1024 bytes
111 = no Rx threshold. The RTL8169 begins the transfer of data after
having received a whole packet in the FIFO.
12:11 -
-
Reserved
cont...
