RTL8169
2002/03/27
Rev.1.21
16
6.2 FLASH: Flash Memory Read/Write
(Offset 0030h-0033h, R)
Bit
R/W
Symbol
Description
31:24 R/W
MD7-MD0
Flash Memory Data Bus:
These bits set and reflect the state of the
MD7 - MD0 pins during the write and read process respectively.
23:21 -
-
Reserved
20 W
ROMCSB
Chip Select:
This bit sets the state of the ROMCSB pin.
19 W
OEB
Output Enable:
This bit sets the state of the OEB pin.
18 W
WEB
Write Enable:
This bit sets the state of the WEB pin.
17 W
SWRWEn
Enable software access to flash memory:
1: Enable read/write access to flash memory via software and
disable the EEPROM access during flash memory access via
software.
0: Disable read/write access to flash memory via software.
16:0 W
MA16-MA0
Flash Memory Address Bus:
These bits set the state of the MA16-0
pins.
6.3 ERSR: Early Rx Status
(Offset 0036h, R)
Bit
R/W
Symbol
Description
7:4 -
-
Reserved
3 R
ERGood
Early Rx Good packet:
This bit is set whenever a packet is completely
received and the packet is good. Writing a ‘1’ will clear this bit.
2 R ERBad
Early Rx Bad packet:
This bit is set whenever a packet is completely
received and the packet is bad. Writing a ‘1’ will clear this bit.
1 R
EROVW
Early Rx OverWrite:
This bit is set when the RTL8169's local address
pointer is equal to CAPR. In the early mode, this is different from buffer
overflow. It happens when the RTL8169 detects an Rx error and wants
to fill another packet data from the beginning address of that error
packet. Writing a ‘1’ will clear this bit.
0 R EROK
Early Rx OK:
The power-on value is 0. It is set when the Rx byte count
of the arriving packet exceeds the Rx threshold. After the whole packet
is received, the RTL8169 will set ROK or RER in ISR and clear this bit
simultaneously. Setting this bit will invoke a ROK interrupt.
