RadiSys EPC-9, Hardware Reference Manual, Page: 92 / 168

A-1
A A
Appendix A -
Chipset & I/O Map
The following defines the I/O addresses decoded by the EPC-9. Only the A9-A0 bits
are decoded for the registers between 200h and 3FFh. For the I/O addresses above
8000h, A15 and A9-A0 are decoded.
First (8-bit) DMA controller
I/O Addr Functional group Usage
000 DMA Channel 0 address
001 Channel 0 count
002 Channel 1 address
003 Channel 1 count
004 Channel 2 address
005 Channel 2 count
006 Channel 3 address
007 Channel 3 count
008 Command/status
009 DMA request
00A Command register (R)
Single-bit DMA req mask(W)
00B Mode
00C Set byte pointer (R)
Clear byte pointer (W)
00D Temporary register (R)
Master clear (W)
00E Clear mode reg counter (R)
Clear all DMA req mask(W)
00F All DMA request mask
First Interrupt controller
I/O Addr Functional group Usage
020 Interrupt controller 1 Port 0
021 Port 1
Counter-Timer functions
I/O Addr Functional group Usage
040 Timer Counter 0
041 Counter 1
042 Counter 2
043 Control (W)
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