Registers
E
E
E-11
MLK
This bit is used for synchronization of messages from multiple senders,
something not provided for in the VXI specification. If 1, the message
register can be locked for the sending of a message. If 0, the message
register has been locked. See the discussion of message sending protocol,
below.
WRC
This bit is a read-only copy of the WRY bit.
FSIG
Defined only when SIG=1, in which case FSIG is the number (0 or 1) of the
register in the FIFO holding the earliest signal.
LSIG
Defined only when SIG=1, in which case LSIG is the number (0 or 1) of the
register in the FIFO holding the most recent signal.
DOR
RAM bit available to software for VXI communication protocols.
DIR
RAM bit available to software for VXI communication protocols.
ERR
RAM bit available to software for VXI communication protocols.
RRY
Read ready. A 1 denotes that the message registers contain outgoing data to
be read by another device. RRY is cleared when the message-low register is
read from VME. RRY can only be set by writing to this register from the PC
port.
WRY
Write ready. If set, the message registers are armed for an incoming mes-
sage. When a write occurs into the message-low register, WRY is cleared
and the MSGR interrupt condition is asserted. Wry can only be set by
writing to this register from the PC port.
FSIG and LSIG are not used for programming. They are read-only bits used for tests
during manufacturing.
The protocol for sending a message, when there are multiple potential senders, is as
follows:
Read the Alternate Response register (offset 2A).
If both WRY and MLK are 1, then proceed to send the message.
If not, repeat reads until both WRY and MLK are 1.
For 16-bit messages, write into the Message Low register.
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