EPC-9 Hardware Reference
E
E
E-8
value of an IACK cycle. This is useful because, for some reason, the Universe chip
strips off the upper 8 bits and flips bit 0. Each IACK Latch register corresponds to a
different VME interrupt.
VXI Register Details
The addresses shown are offsets relative to a base address. See VXI Register Base
Address Decoding, below, for the method for determining the base address.
If a bit is shown as 0 or 1, the bit is a ROM bit, and writing to it has no effect. Except
as otherwise noted below, all registers and bit values can be read and written.
ID/ULA Register (offset 0h)
ECh
0h
ID/ULA Register (offset 1h)
8Fh
1h
This register adheres to the VXIbus specification. It defines EPC-9 as a message-
based device and the manufacturer as RadiSys. When read, the ID is returned. When
written, the lower 8 bits define the unique logical address (ULA). The upper 8 bits are
ignored. The ULA is not valid as an addressing mechanism until the register is
written the first time. Until then, one must use the MODID address mechanism (i.e.,
ULA of FFh with MODID asserted) to address the VXI registers.
Device Type Register (offset 2h)
MM
2h
Device Type Register (offset 3h)
0001 000S
3h
These registers adhere to the VXIbus specification. The value defines EPC-9 as
having a model code of 10MMh if it is a slot 0 controller and 11MMh if it is not a slot
0 controller. MM is the value in the Model register.
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