Registers
E
E
E-5
VME Event Enable Register (8153h)
LRRY
LWRY
11
IACK
MSGIE
SIGIE
WDTIE
8153h
The LRRY and LWRY are used as latching bits which hold the event of a RRY or
WRY transition from a high to a low state. Thus if RRY transitions from a high to a
low state (indicates a read of the VME message register occured), then LRRY will be
set to a one. The same is true for the LWRY in the instance of a write to the message
register. These bits can individually be reset to a zero state by writing a one to the
respective bit field. Thus to clear LRRY, write a one in the MSB by ORing the current
state of the register with the value of 80h. In the case of the LWRY a 40h would be
ORed with the current value of the register.
If the MSGE bit is asserted and LRRY or LWRY is set, then an interrupt from the
FPGA will be signaled to the processor. (i.e., AT interrupt 10 will be asserted to the
processor)
The IACK bit indicates when an interrupt acknowedge is occuring. It indicates the
actual value of the IACK signal line on the VME bus.
These bits are a mask of the interrupt conditions in the event state register. A one
denotes that the corresponding event is enabled as an interrupt. If any bit in this
register is a one, and the corresponding bit in the event state register is a zero, the INT
pin is asserted. Software may then examine the interrupt and event state registers to
determine the cause. Reset clears this register.
Status/Control Register (8154h)
SRIE
1
SYSC
1
RDY
PASS
NOSF
RSTP
8154h
Status/Control Register (8155h)
0
MODI
SYSR
1
1
1
1
1
8155h
These registers adhere to the VXIbus specification and also contains EPC-9 specific
bits. Bits RSTP and NOSF are writeable only from the VME port. Bits SRIE, RDY,
PASS, SYSR are writeable only from the PC Port. All bits are readable from both
ports. See the VXI register description for details of each bit definition.
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