EPC-9 Hardware Reference
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For 32-bit messages, write first into Message High register and then into the
Message Low register.
The bits RRY, WRY, ABMH, and MLK in the Response register are altered by
hardware-detected conditions. A read from the Message Low clears RRY. A write
into all or the lower 8 bits of the Message Low register clears WRY. A read from
the VME bus port of the Alternate Response register clears MLK if WRY is set. A
read or write to all or the lower 8 bits of the Message High register clears ABMH. A
read from the Alternate Response register also returns the value in the Response
register. Note that the Alternate Response register is accessed at offset 0x2A from the
VME A16 base address of these registers.
LOCK, RRIE, MLK, ABMH, DIR, DOR, ERR can be set or cleared by using a write
to the response register. RRY and WRY may only set via a write to the Response
register. For these two bits, a 0 written into the respective bit position will not change
the value of the register bit. A 1 written into the respective bit position will set the
value of the register bit to 1.
Supporting software on the controller must be aware of how to set the bits initially.
The valid states are:
RRY
WRY
MLK
State
X
1
1
Write ready (awaiting incoming msg)
X
1
0
Write ready, locked by a sender
1
X
X
Read ready (outgoing data present)
0
0
X
Not ready for write or read
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