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Connectors

C

C

C-9

  EIDE (Secondary) Connector JP3

The Secondary EIDE Connector is a male 40-pin header designated JP3, located at the
front of the bottom edge of the Main I/O board. The pins and signals are defined in
the following table:

Pin

Signal

Pin

Signal

1

~RST

2

GND

3

D7

4

D8

5

D6

6

D9

7

D5

8

D10

9

D4

10

D11

11

D3

12

D12

13

D2

14

D13

15

D1

16

D14

17

D0

18

D15

19

GND

20

N.C.

21

DRQ

22

GND

23

~IOW

24

GND

25

~IOR

26

GND

27

IORDY

28

SPU

29

DAK

30

GND

31

IRQ

32

IOCS16

33

A1

34

N.C.

35

A0

36

A2

37

CS0

38

CS1

39

ACT

40

GND

Table C-10. Secondary EIDE Connector.

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Summary of Contents for EPC-9

Page 1: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

Page 2: ...____ 07 0877 00 April 1997 EPC 9 Hardware Reference RadiSys Corporation 5445 NE Dawson Creek Drive Hillsboro OR 97124 Phone 503 615 1100 Fax 503 615 1150 http www radisys com Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 3: ...s Machines Corporation Intel and Pentium are registered trademarks of Intel Corp Microsoft and MS DOS are registered trademarks of Microsoft Corporation Motorola is a registered trademark of Motorola Inc PhoenixBIOS and NuBIOS are trademarks of Phoenix Technologies Ltd RadiSys and EPC are registered trademarks and EPConnect is a trademark of RadiSys Corporation April 1997 Copyright 1994 1995 1996 ...

Page 4: ... Selecting the EPC 9 Slot Location 2 3 Installing the VMEbus Backplane Jumpers 2 3 EPC 9 Insertion 2 8 Connecting Peripherals to the EPC 9 2 9 Remaining Steps 2 9 CHAPTER 3 BIOS Configuration Introduction 3 1 BIOS Setup Screens 3 1 Main BIOS Setup Menu 3 3 IDE Adapter Sub Menus 3 6 Memory Cache Sub Menu 3 9 Memory Shadow Sub Menu 3 10 Boot Options Sub Menu 3 12 Keyboard Features Sub Menu 3 14 Adva...

Page 5: ...5 2 VMEbus Master Accesses 5 3 VMEbus Locked Accesses RMW 5 4 VMEbus Interrupter 5 4 VMEbus Access to Universe Registers 5 5 PCIbus Access to Universe Registers 5 5 For More Programming Information 5 5 Chapter 6 Support and Service In North America 6 1 Technical Support 6 1 World Wide Web 6 1 Repair Services 6 2 Warranty Repairs 6 2 Non Warranty Services 6 2 Arranging Service 6 3 Other Countries 6...

Page 6: ... Registers A 5 ECP Registers A 6 VME and Misc A 6 ULA Relative VXI Registers in VME Address Space A 6 Appendix B Interrupts and DMA Channels Interrupts B 1 DMA Channels B 2 Appendix C Connectors and Jumpers Keyboard Connector C 3 Mouse Connector C 3 RS 232 Ports COM A COM B C 4 Parallel Port C 4 SVGA Connector C 5 RJ45 Connector C 5 Dual USB Connector C 6 SCSI 2 Connector C 7 EIDE Primary Connecto...

Page 7: ...XI Register Details E 8 VXI Register Base Address Decoding E 13 Appendix F Glossary F 1 Appendix G SVGA and the PMC 1 Video Module Video Controller Hardware G 1 Installing the PMC 1 SVGA Video Module G 3 Display Drivers and Utilities Software G 5 Cirrus Logic Support G 6 Utility Software G 6 Appendix H Error Messages Diagnosis Boot Failures H 1 Troubleshooting H 3 BIOS Beep Codes H 6 Artisan Techn...

Page 8: ...s Sub Menu 3 18 Figure 3 10 Advanced Chipset Sub Menu 3 20 Figure 3 11 Power Management Menu 3 22 Figure 3 12 EXM Menu 3 27 Figure 3 13 Slot Numbering 3 28 Figure 3 14 VME Setup Menu 3 30 Figure 3 15 Exit Menu 3 32 Figure 4 1 EPC 9 Block Diagram 4 3 Figure 4 2 Flash Boot Device Memory 4 8 Figure 4 3 Replacing the Lithium CMOS Battery 4 10 Figure C 1 EPC 9 Assembly C 1 Figure C 2 EPC 9 Front Panel ...

Page 9: ...t C 3 Table C 2 Mouse Pin Out C 3 Table C 3 DB 9 Pin Out C 4 Table C 4 DB 25 Pin Out C 4 Table C 5 DB 15 Pin Out C 5 Table C 6 RJ 45 Phone Jack Pin Out C 5 Table C 7 Dual USB Connector C 6 Table C 8 SCSI 2 Connector C 7 Table C 9 Primary EIDE Connector C 8 Table C 10 Secondary EIDE Connector C 9 Table C 11 Floppy Disk Drive Connector C 10 Table H 3 Troubleshooting Error Messages H 3 Artisan Techno...

Page 10: ...ity with VMEbus architecture For more information about EPConnect which is a C C programming interface to the Microsoft Windows NT API consult the EPConnect for Windows NT 4 0 Programmer s Reference Guide available from Radisys The information in this manual is organized into the following sections Front Matter Table of Contents List of Figures List of Tables Chapter 1 Product Description Provides...

Page 11: ...d DMA Channels Shows the DMA channel and IRQ assignments to the peripherals supported by the EPC 9 Appendix C Connectors Details the location form and pin outs of the connectors used in the EPC 9 Appendix D Subplanes Describes the use of the interconnect subplanes used to connect the EPC 9 with EXM expansion modules Appendix E Registers Maps the address space used by EPC 9 and VMEbus registers App...

Page 12: ... 16 32 64 128 or 256MB of memory using dual socket SODIMM DRAM Standard front panel PC peripheral interfaces include two RS232 serial ports an IEEE 1284 bi directional parallel port two USB ports a PCI based SCSI 2 interface and 10BASE T 100BASE TX Ethernet ports all with standard interface connectors The mouse and keyboard connectors are PS 2 style All other standard PC architectural features inc...

Page 13: ... interface 10BASE T and 100BASE TX Ethernet interfaces The interface is based on the Digital 21143 Ethernet controller Interface configuration emulation mode and address interrupt control is software controlled A watchdog timer This device can be configured to generate a VMEbus SYSFAIL signal and either halt or perform a warm reboot of the processor depending on a BIOS setup option The timer is im...

Page 14: ...egisters which maximizes performance in a multitasking or interrupt driven environment Programmable hardware byte swapping is provided for ease of communication with other processor architectures that may share the VMEbus All the VMEbus address spaces can be addressed from both protected mode and real mode operating systems The EPC 9 can generate or respond to all 7 standard VMEbus interrupts and ...

Page 15: ...ese registers are implemented in a proprietary gate array and mapped into the VMEbus A16 address space and include a device type identifier register bus status and control registers and a register based message passing facility Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 16: ...d air derated 2 C per 1000 ft 300 m over 6600 ft 2000 m 2 C per hour max excursion gradient storage 40 C 85 C 5 C per hour max excursion gradient Humidity operating 5 95 noncondensing storage 5 95 noncondensing Altitude operating 0 10 000 ft 3000 m storage 0 40 000 ft 12 000 m Vibration operating 2 5 g acceleration over 5 300 Hz sine wave 1 oct min sine sweep storage 5 g acceleration over 5 2K Hz ...

Page 17: ...ains other specifications Characteristic Value Mechanical Weight with PMC 1 2 7 lb 1 3 kg Dimensions two slot 6U VMEbus module Safety UL 1244 IEC 1010 1 1990 Incl Amend 1 1992 EN61010 1993 CSA C22 1010 1 1992 EMC CE Mark CISPR 11 1990 EN 55011 1991 Group 1 Class A IEC 801 2 1991 EN50082 1 1992 4kV CD 8kV AD IEC 801 3 1984 EN50082 1 1992 3V m IEC 801 4 1988 EN50082 1 1992 1kV Power Line EMC Directi...

Page 18: ...RI system controller SYSCLK IACK bus grant daisy chain drivers and bus time out error BERR VXI device type message based protocols servant commander master interrupter manufacturer code 4076 RadiSys Corporation model code 101Fh if configured for slot 0 111Fh if configured for other than slot 0 Table 1 3 continued Additional EPC 9 Specifications Artisan Technology Group Quality Instrumentation Guar...

Page 19: ...EPC 9 Hardware Reference 1 1 1 10 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 20: ...em DO NOT REMOVE THE EPC 9 MODULE FROM ITS ANTI STATIC BAG UNLESS YOU ARE IN A STATIC FREE ENVIRONMENT The EPC 9 like most electronic devices is susceptible to electrostatic discharge ESD damage ESD damage is not always immediately obvious It can cause a partial breakdown in semiconductor devices that might not result in immediate failure DURING ALL OF THIS INSTALLATION PROCESS MAKE SURE THAT POWE...

Page 21: ...tionality when it is inserted in Slot 1 The Slot 1 configuration option is enabled automatically by detecting the VMEbus BG3IN signal if the board is the system controller Slot 1 If BG3IN is sampled low immediately after reset the EPC 9 is installed in Slot 1 and becomes the system controller The EPC 9 will always power up in non system controller mode and sample BG3IN to determine whether or not ...

Page 22: ...l of the EXMs and PMCs to be used check the total power requirements against the power supply ratings of your VMEbus system and the other modules to ensure that the power supply can handle the total power required Once you have determined the EPC 9 subsystem physical location in the chassis the VMEbus backplane must be jumpered appropriately as described in the following section Installing the VME...

Page 23: ...n to BG1Out IackIn to IackOut either through the board in that slot or by jumpers Boards that meet VMEbus specifications correctly handle the signals and do not need backplane jumpers However many early designs may not handle any of these signals Check the manual for each board to be installed to determine if these signals are passed through correctly If these signals are not handled correctly by ...

Page 24: ...o additional EXM modules and an EXP MX storage module Note that the use of an EXP MX storage module requires that the Local Bus IDE Controller field in the Integrated Peripherals BIOS setup menu be set to Disabled See Chapter 3 BIOS Configuration for more information Note that the left most slot does not require any jumpers All of the other slots occupied by the subsystem require that all five jum...

Page 25: ...lane the most common location is in the middle of the J1 connector as shown in Figure 2 3 The connector may have wire wrap tails on all pins or just on the bus grant and IACK pins Stake pins front or rear can also be located adjacent to the slot being jumpered as shown in Figure 2 4 Typically the stake pins are located between the slot being jumpered and the next lower numbered slot e g jumpers fo...

Page 26: ...Figure 2 4 VMEbus Jumpers on Front Stake Pins Consult your VMEbus chassis reference manual or contact the chassis manufacturer if you are unsure where to jumper your particular system Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 27: ...NES WHEN HANDLING OR INSERTING THE EPC 9 MODULE AVOID TOUCHING THE CIRCUIT BOARD AND CONNECTOR PINS AND MAKE SURE THE ENVIRONMENT IS STATIC FREE Make sure the ejector handles are in the normal non eject position Push the top handle down and the bottom handle up so that the handles are not tilted Slide the EPC 9 module into the left most slot occupied by the subplane Use firm pressure on the handle...

Page 28: ... for the EPC 9 front panel connectors are specified in Appendix C Connectors and Jumpers SCSI Termination When you configure SCSI peripherals to work with the EPC 9 you need to consider the placement of the EPC 9 in the SCSI chain The EPC 9 is must be the last device in the SCSI chain and thus is terminated Remaining Steps The remaining configuration steps may include BIOS configuration driver sof...

Page 29: ...EPC 9 Hardware Reference 2 10 2 2 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 30: ...s configured will either pause or attempt to continue Refer to Appendix H Error Messages Diagnosis BIOS Setup Screens The EPC 9 s BIOS contains a setup function to display and modify the system configuration This information is maintained in the EPC 9 s nonvolatile CMOS RAM and is used by the BIOS to initialize the EPC 9 hardware The BIOS Setup can only be entered during the system reset process f...

Page 31: ...enu and then return your active field is always at the beginning of the menu If you select a sub menu and then return to the main menu you return to that sub menu heading Fields with a triangle to the left are actually sub menu headings press Enter when the cursor rests on one of these headings to reach that sub menu For most fields position the cursor at the field and from the numeric keypad pres...

Page 32: ... seconds or from months to days to years There is no default value PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help System Date 03 01 96 IDE Adapter 0 Master C 704 Mb Video System EGA VGA Memory Cache Memory Shadow System Memory 640 KB Extended Memory 31 MB F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Val...

Page 33: ...formation Memory Shadow Sub Menu The term Memory Shadow refers to the technique of copying information from an extension ROM into DRAM and accessing it in this alternate memory location The EPC 9 restricts what memory is available for shadowing because of the special requirements for SCSI and the Universe PCI VME bridge See Memory Shadow Sub Menu for more information Boot Sequence Sub Menu The Boo...

Page 34: ...ount of conventional memory below 1MB No user interaction is required Extended Memory This field is not editable and displays the amount of extended memory above 1MB No user interaction is required Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 35: ...nix Technologies Ltd Item Specific Help F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Values Tab Shift Tab or Enter selects field Autotype Fixed Disk Press Enter IDE Adapter 0 Master C 704Mb Multi Sector Transfers 16 sectors Write Precomp None Sectors Track 63 Heads 16 Cylinders 1365 Type User 704 Mb Transfer Mode Fast DMA F 32 Bit I O ...

Page 36: ...ut adding a number of seconds to the duration of the POST Note that there are some restrictions when setting up devices on the EPC 9 If you plan to boot from a non IDE device such as a SCSI hard disk set the C drive type as None to allow the BIOS extension to find and boot from the bootable device with the lowest SCSI ID number Multi Sector Transfers This option allows the user to configure the Sy...

Page 37: ...This option selects the mode that the System BIOS uses to access the hard disk The selections are Standard default Fast PIO 1 Fast PIO 2 Fast PIO 3 Fast PIO 4 Fast DMA A Fast DMA B Fast DMA F Older hard disks only support Standard Newer hard disks adhering to Fast ATA or Enhanced IDE specifications may support the fast programmed I O or DMA modes Note that autotyping may change this value dependin...

Page 38: ...hing of the System BIOS area in the 0E0000h through 0FFFFFh DRAM area The default is Enabled PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Values Tab Shift Tab or Enter selects field External Cache Enabled Memory Cache Cache System BIOS Area Enabled Cache Vi...

Page 39: ...enerally increases system performance if many calls to the BIOS extensions are made The Memory Shadow Sub Menu is shown below The shadow regions should be used only if an EXMbus card is installed in the system that contains a BIOS extension ROM although there is no effect on the system if a PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help F1 Help Select Item Change V...

Page 40: ...to be shadowed is larger than 16KB System Shadow This option is not editable since the System BIOS is always shadowed Video Shadow Enable this option to increase video BIOS performance The default is Enabled Shadow Memory Regions These options enable or disable shadowing for the associated memory region The default is Disabled Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOUR...

Page 41: ...mpt Enabled Boot Sequence A then C Summary Screen Enabled Extended Memory Test Enabled Figure 3 6 Boot Options Sub Menu Boot Delay Use this option to set the system to delay booting for a time period from 0 through 255 seconds This allows for long start up times on boot devices that spin up slowly The default is 0 seconds Boot Sequence This option is used to define how the system treats floppy dri...

Page 42: ...ages that display Note that this option only affects those errors defined as boot failures See AppendixH Error Messages and Diagnosis for a list of those failures are defined as boot failures that are configured to halt the system The default is Enabled Floppy Check This option is used to enable or disable the floppy drive search during the boot To speed up booting the floppy check should be disab...

Page 43: ...lues Tab Shift Tab or Enter selects field NumLock Off Keyboard Features Keyboard auto repeat delay 1 4 sec Keyboard auto repeat rate 30 sec Key Click Disabled Figure 3 7 Keyboard Features Sub Menu Numlock Use this option to enable or disable the Numlock feature of the keyboard Numlock on enables the use of the keypad numbers The default is Off Key Click Use this option to enable or disable the key...

Page 44: ...d 30 sec The default rate is 30 sec Keyboard auto repeat delay Use this option to set the delay between when a key is pressed and when the auto repeat feature begins The options are 1 4 sec 1 2 sec 3 4 sec and 1 sec The default delay is 1 4 sec When you are finished with this menu press ESC to exit back to the Main BIOS Setup screen Artisan Technology Group Quality Instrumentation Guaranteed 888 8...

Page 45: ...s Setting items on this menu to incorrect values may cause your system to malfunction Advanced Chipset Control Plug Play O S No Reset Configuration Data No Halt on watchdog reset Disabled Large Disk Access Mode DOS Main Advanced Power EXM VME Exit User BIOS Extensions Destination Address D0000H BIOS Extension Offset in FBD Disabled BIOS Extension Size 2000H BIOS Extension 1 Figure 3 8 Advanced Men...

Page 46: ...is Disabled Large Disk Access Mode If a hard disk larger than 528MB is being used this selection should be set to DOS if running MS DOS or set to Other if using a different operating system When set to DOS this selection causes the System BIOS to perform cylinder head translation if the drive is configured in Setup to have more than 1024 cylinders This allows MS DOS systems to use hard disks up to...

Page 47: ...ter Select Sub Menu F10 Previous Values Tab Shift Tab or Enter selects field COM A 3F8 IRQ4 Integrated Peripherals LPT Mode ECP LPT port 378 IRQ7 COM B 2F8 IRQ3 Diskette Controller Enabled Local Bus IDE adapter Both Onboard Ethernet Controller Enabled Onboard SCSI Controller Enabled Figure 3 9 Integrated Peripherals Sub Menu COM A This option is used to configure the serial port labeled on the fro...

Page 48: ...s The default I O base and IRQ for this LPT port are 378h IRQ7 LPT Mode This option sets the mode under which the LPT port operates The selections are Output only Bi directional ECP Diskette Controller This option enables or disables the onboard floppy disk controller The default is Enabled Local Bus IDE adapter This option enables or disables the onboard PCIbus IDE hard disk controller This optio...

Page 49: ...w PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Values Tab Shift Tab or Enter selects field DRAM Speed 70 ns Advanced Chipset Control 16 bit I O Recovery 4 5 8 bit I O Recovery 4 5 DMA Aliasing Enabled IRQ 12 used by PS 2 Mouse ECC Parity Config Disabled Fig...

Page 50: ...from 3 5 through 7 5 SYSCLKs in 1 SYSCLK increments The default is 4 5 SYSCLKs IRQ 12 used by This option selects the routing of IRQ12 For systems without a PS 2 mouse this option may be set to ISA bus to allow an ISAbus peripheral to use this interrupt line Systems using a PS 2 mouse must have this option set to PS 2 Mouse for the mouse to operate correctly Since the EPC 9 has a PS 2 mouse connec...

Page 51: ...nagement APM The default is Enabled PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Values Tab Shift Tab or Enter selects field APM Enabled Standby Timeout 15 min Power Savings Disabled Suspend Timeout 15 min Fixed Disk Timeout Disabled CRT OFF in Standby Stan...

Page 52: ...e Suspend Mode The options are the same as for the Standby Timeout shown above The default is 15 min Standby CPU Speed Use this option to enable or disable the changing of the CPU speed based upon the current power management state The options are Disabled LOW MEDIUM HIGH and MAX The default is MEDIUM Fixed Disk Timeout Use this option to enable and set the fixed disk access inactivity period requ...

Page 53: ...he specified IRQ A Standby Break Event allows the system to run at full speed for the duration of the specified IRQ Note No such event is associated with IRQ2 IRQ0 Use this option to enable or disable the Standby Break Event for IRQ0 The options are Disabled and Auto The default is Disabled IRQ1 Use this option to enable or disable the Standby Break Event for IRQ1 The options are Disabled and Auto...

Page 54: ...for IRQ8 The options are Disabled and Auto The default is Disabled IRQ9 Use this option to enable or disable the Standby Break Event for IRQ9 The options are Disabled and Auto The default is Disabled IRQ10 Use this option to enable or disable the Standby Break Event for IRQ10 The options are Disabled and Auto The default is Disabled IRQ11 Use this option to enable or disable the Standby Break Even...

Page 55: ...abled Standby Wakeup Events Use this option to cause a Standby Wakeup Event based on keyboard or mouse activity A Standby Wakeup Event allows the system to return to full speed Keyboard Use this option to enable or disable the Standby Wakeup Event based on keyboard activity The default is Enabled Mouse Use this option to select the mouse IRQ binding for mouse activity detection for power managemen...

Page 56: ... the ID set with this option does not agree with the ID of the card actually installed in the slot an EXM configuration error occurs and the card is not configured For a slot with no EXM card installed enter 0FFh the default value PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help EXM Slot 0 F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter...

Page 57: ...d option byte value for the EXM card intended to reside in this slot Option byte 2 is defined by the particular EXM card installed The proper value of this option for a slot with no EXM card installed is not defined The value typically used is 00h the default value NOTE Since the EPC 9 uses existing EXM backplanes the first 2 slots will be covered by the PMC card s To compensate for this EXM slot ...

Page 58: ...RQ3 and IRQ4 should not be used if either onboard COM port is being used IRQ 15 should not be used if the secondary IDE channel is being used IRQ9 is used by the Universe chip 2 Use DMA channels 1 3 6 and 7 3 Do not select I O addresses that conflict with those in the EPC 9 A com plete list appears in Appendix A For instance I O addresses in the 300 33F range can be used 4 If the EXM needs to use ...

Page 59: ...in configures the arbiter to scan the bus request lines from highest priority down to lowest priority and grant the bus to the first requester it finds Selecting Priority configures the arbiter to grant the bus to the highest priority requester at any time The default is Round Robin PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help Arbitration Priority 0 F1 Help Selec...

Page 60: ...bus when its current bus access has completed This has the effect of increasing the performance of other bus masters Selecting RWD Release When Done causes the EPC 9 to behave the same as RONR except it does not delay 50ns before attempting to regain control of the bus The default is ROR VME Unique Logical Address This option is used to select the ULA for the EPC 9 This logical address is used to ...

Page 61: ... used to reset the Setup values to the original default values that were set at the factory before any suppliers or other end users made changes PhoenixBIOS Setup Copyright 1985 96 Phoenix Technologies Ltd Item Specific Help Save Changes Exit F1 Help Select Item Change Values F9 Setup Defaults ESC Exit Select Menu Enter Select Sub Menu F10 Previous Values Tab Shift Tab or Enter selects field Main ...

Page 62: ... session started Save Changes This option is used to save the edits made during a session Exit Update BIOS This option is used to initiate a System BIOS update NOTE Do not select this exit option unless you have obtained BIOS update replacement software from your supplier and have reviewed the documentation and procedures provided with that distribution If you select this option by mistake reset t...

Page 63: ...EPC 9 Hardware Reference 3 3 3 34 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 64: ...C conforming to IEEE specification P1386 1 PMC The RadiSys PMC 1 Video Module provides VGA resolutions to 1280 x 1024 with 256 colors Figure 4 1 provides a diagrammatic overview of the system functional blocks Most of the standard functions of the PC architecture are embodied in the Intel 82430HX T2 PCI based chipset PC peripheral interfaces for monitor keyboard mouse two serial ports a parallel p...

Page 65: ... includes special PAL based VME byte order swapping hardware to deal with the difference between Intel and Motorola data representations Byte swapping of D16 and D32 accesses only occurs when desired EPC 9 Organization Block Diagram The block diagram in Figure 4 1 shows the division and interconnection of EPC 9 functions These are described below Artisan Technology Group Quality Instrumentation Gu...

Page 66: ...Theory of Operation 4 4 4 3 Figure 4 1 EPC 9 Block Diagram Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 67: ...supports up to 256MB of 60 or 70 ns Fast Page Mode or EDO DRAM in two dual 72 pin SODIMM sockets The CPU memory bus is 64 bits wide so the SODIMM sockets must be populated with identical pairs of 32 bit DRAM modules The TXC controller generates all of the required control signals such as RAS CAS and WE as well as the multiplexed addresses for the DRAM array Upgrading Main System Memory At the time...

Page 68: ... 0E4000 0FFFFF Shadowed system BIOS Watchdog Timer The watchdog timer is a binary counter which upon overflow will signal a watchdog timer event The counter will cause a watchdog event after approximately 125 ms 1 second or 8 seconds depending on the value of WDTV bits 2 and 1 in register 8150h if the application software does not reset the timer An I O read to address 8150h resets the counter If ...

Page 69: ...rs WDT bit in the VME event register bit 0 of register 8153h Application software that utilizes this timer should take care to reset the counter just prior to enabling the interrupt bit in register 8155h This will inhibit a spurious timer event from occurring just after enabling the timer Flash Boot Device The Intel E28F004BX T is used as a Flash Boot Device FBD This is flash updatable BIOS contai...

Page 70: ...yboard controller uses interrupt IRQ1 and the mouse uses IRQ12 An adapter cable is shipped with the EPC 9 to allow standard PC AT keyboards with larger 5 pin connectors to plug into PS 2 connectors BIOS ROM and ROM Shadowing The EPC 9 utilizes a Flash Boot Device FBD as its BIOS ROM The BIOS ROM is mapped into the top of the processor s 32 bit address space The BIOS consists of a 16 KByte boot blo...

Page 71: ...00h FFFA0000h Main Block 2 128 KB ESCD 4KB 3FFFFh 20000h FFF80000h Main Block 1 128 KB CMOS Data 1KB 1FFFFh 00000h Figure 4 2 Flash Boot Device Memory The BIOS initialization software copies the ROM contents into DRAM a process called shadowing at addresses 0E0000h 0FFFFFh The VGA BIOS is copied into 0C0000h 0C7FFFh of DRAM After copying into these areas the BIOS write protects them Subsequent wri...

Page 72: ...eline wander compensation 10 100 switching and clock generation and recovery This controller uses PCI INTB and Bus Arbitration channel 0 which are shared with PMC slot 0 It is configured through the PCI Configuration Space The internal Ethernet controller must be disabled via the BIOS setup Integrated Peripherals menu whenever a PMC requiring PCI bus mastering is installed in PMC slot 0 The Ethern...

Page 73: ...and remove the EPC 9 from the VME chassis IMPORTANT You should perform all of these steps in a static free or ESD protected environment 1 Refer to the procedures in Appendix G SVGA and the PMC 1 Video Module and remove the PMC 1 then remove the EPC 9 Carrier Board 2 Locate the battery then lift the top retaining contact clip slightly and slide the old battery out in the direction shown in Figure 4...

Page 74: ...ion products USB Ports The Universal Serial Bus USB controller is a host hub controller and moves data between the main system memory and devices on the serial bus The USB controller also includes the first level hub This permits connection of two USB peripheral devices directly to the PIIX3 without an external hub If more devices are required an external hub can be connected to any one of the bui...

Page 75: ...face on the EPC 9 is controlled by a single chip the Tundra Semiconductor Universe PCI VME bridge The Universe controls a layer of buffers between it and the VMEbus and has a glueless interface to the PCIbus The VMEbus interface uses both the P1 and P2 connectors to allow an addressing space of A16 A24 A32 with D08 D16 and D32 data accesses It uses PCI INTD and bus mastering lines The VME bus inte...

Page 76: ... Video Module for SVGA support The PMC 1 uses a Cirrus Logic CL GD5446 The video module connects to the PCIbus and has 2MB of VGA memory and resolutions from 640 x 480 256 colors to 1280 x 1024 256 colors The PMC 1 is described in full detail in Appendix G SVGA and the PMC 1 Video Module Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 77: ...d remains on until the initial power on self tests have completed RUN green This LED is lit whenever a write access to DRAM is made This provides a normally lit LED indicating that the CPU is operating This LED is not lit if the CPU is halted or is executing entirely out of the on chip cache MASTER green This LED is lit whenever the EPC 9 is bus master SCSI green This LED is lit when the SCSI port...

Page 78: ...dware reset The system runs the power on self tests and reboots the operating system Ctrl Alt Del Warm software reset This keyboard sequence is also called a warm boot The EPC 9 does not reinitialize all of the processor s hardware However the operating system is reloaded VMEbus SYSRESET Warm hardware reset The EPC 9 can be software configured to respond or not respond to the VMEbus SYSRESET line ...

Page 79: ... such as to EXM modules and the EXP MX Mass Storage module These EXM interface signals are not passed through to the VMEbus Further information on the EXM expansion interface its connectors and standards for building EXMs is available upon request Notes on Byte Ordering There are two fundamentally different ways of storing numerical values in byte loca tions in memory Little endian characteristic ...

Page 80: ...image You use little endian images to map VMEbus memory to another Intel processor and big endian images to map VMEbus memory to a Motorola processor The Slave Image Control Registers are described in the Universe User s Manual available on the world wide web at http www newbridge com Tundra Products Bus BPI Univdn html The particular control registers for each image are described in Appendix A Sl...

Page 81: ...ible by 4 Failure to properly align addresses results in scrambled data Although the VMEbus address must be boundary aligned to match the data width word or double word the Pentium address does not need to be boundary aligned You must also consider the compiler you are using because some compilers produce two 16 bit accesses when a 32 bit access is desired resulting in scrambled data When transfer...

Page 82: ...ly with the VMEbus registers Register Initialization At power on self test POST time a subset of the VME registers is initialized by the BIOS The Universe chip then initializes the remainder of the VME registers This is controlled by how the Universe chip is programmed Programming the Universe The Universe chip can become system controller if the EPC 9 is in slot 1 It does this by sampling the VME...

Page 83: ... VMEbus Timeout A programmable bus timer allows the VMEbus timeout period to be selected via the MISC_CTL register It can be programmed to 16 us 32 us 64 us 128 us 256 us 512 us 1024 us or disabled The default setting is 64 us If a bus transaction times out the timer asserts the VMEbus BERR signal VMEbus Requester The Universe is software configurable to request bus ownership on all VMEbus request...

Page 84: ... in the LSIn_CTL LSIn_BS LSIn_BD and LSIn_TO registers of the Universe chip Please refer to the Universe User Manual for programming details VMEbus block transfers are supported by the Universe using its on chip DMA controller The EPC 9 can respond as a VMEbus Slave in either A24 or A32 address spaces It responds to either D08 D16 or D32 accesses Read accesses from the VMEbus to onboard memory may...

Page 85: ...MEbus IRQ pins PCI bus errors VMEbus errors DMA interrupts Software interrupts If a software and a hardware source are both mapped to the same IRQ the software source has higher priority When an IACK cycle on the VMEbus is detected that matches an interrupt level that the EPC 9 is asserting and the IACKIN daisy chain is asserted into the EPC 9 the Universe responds by supplying an 8 bit STATUS ID ...

Page 86: ...ignal on a Configuration Space access Since the Universe registers consume a 4K block of memory only the first 256 registers can be accessed through Configuration Space The remaining registers must be accessed through memory or I O space This 4KB block is also larger than the available area left in the I O space Therefore the registers are memory mapped The base address of the registers must resid...

Page 87: ...EPC 9 Hardware Reference 5 6 5 5 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 88: ...espond by e mail phone or FAX by the next business day Technical support services are designed for customers who have purchased their products from RadiSys or an authorized sales representative If your RadiSys product is part of a piece of OEM equipment or was integrated by someone else as part of a system support will be better provided by the OEM or system vendor that did the integration and und...

Page 89: ...cturing defects during the warranty period See the warranty information at the front of this manual Products without fault sent in for warranty repair will be subject to a recertification charge Extended warranties are available at a standard price for any product still under original warranty RadiSys will gladly quote prices for extended warranties on products with lapsed original warranties cont...

Page 90: ...with a description of the problem A technical support representative will issue a Returned Materials Authorization RMA number a code number by which RadiSys tracks the product while it is being processed Once you receive the RMA number follow the instructions of the technical support representative and return the product to RadiSys freight prepaid Mark the RMA number clearly on the exterior of the...

Page 91: ...e web site to contact us or contact the sales organization from which you purchased your RadiSys product for service and support The RadiSys world wide web URL is http www radisys com Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 92: ...unt 006 Channel 3 address 007 Channel 3 count 008 Command status 009 DMA request 00A Command register R Single bit DMA req mask W 00B Mode 00C Set byte pointer R Clear byte pointer W 00D Temporary register R Master clear W 00E Clear mode reg counter R Clear all DMA req mask W 00F All DMA request mask First Interrupt controller I O Addr Functional group Usage 020 Interrupt controller 1 Port 0 021 P...

Page 93: ...f week 7 date of month 8 month 9 year A status A B status B C status C D status D E 3F RAM Phoenix NuBIOS I O Addr Usage 080 Phoenix BIOS Status Information DMA Page Registers I O Addr Functional group Usage 081 DMA Channel 2 page register 082 Channel 3 page register 083 Channel 1 page register 087 Channel 0 page register 089 Channel 6 page register 08A Channel 7 page register 08B Channel 5 page r...

Page 94: ... group Usage 0C0 DMA Channel 4 address 0C2 Channel 4 count 0C4 Channel 5 address 0C6 Channel 5 count 0C8 Channel 6 address 0CA Channel 6 count 0CC Channel 7 address 0CE Channel 7 count 0D0 Command status 0D2 DMA request 0D4 Command register R Single bit DMA req mask W 0D6 Mode 0D8 Set byte pointer R Clear byte pointer W 0DA Temporary register R Master clear W 0DC Clear mode reg counter R Clear all...

Page 95: ...ge 2F8 COM B serial port Receiver transmitter buffer Baud rate divisor latch LSB 2F9 Interrupt enable register Baud rate divisor latch MSB 2FA Interrupt ID register 2FB Line control register 2FC Modem control register 2FD Line status register 2FE Modem status register Parallel I O LPT1 Port I O Addr Functional group Usage 378 LPT1 parallel port Printer data register 379 Printer status register 37A...

Page 96: ...s controller data 3D4 CRT controller index 3D5 CRT controller data 3DA Feature control pinput status 3F0 Configuration 37C651 Super I O Combo chip 3F1 Configuration 37C651 Super I O Combo chip 46E8 VGA Adapter Sleep Serial I O COM A Port I O Addr Functional group Usage 3F8 COM A serial port Receiver transmitter buffer Baud rate divisor latch LSB 3F9 Interrupt enable register Baud rate divisor latc...

Page 97: ... control register 8156 Model register 8158 8159 Signal FIFO register 8162 8163 IACK latch 1 register 8164 8165 IACK latch 2 register l 8166 8167 IACK latch 3 register 8168 8169 IACK latch 4 register 816A 816B IACK latch 5 register 816C 816D IACK latch 6 register 816E 816F IACK latch 7 register ULA Relative VXI Registers in VME Address Space I O Addr Functional group Usage 0 1 VXI ID ULA register 2...

Page 98: ...ed IRQ7 LPT1 parallel port IRQ8 real time clock IRQ9 Universe Bridge routed to INTD IRQ10 One of 11 interrupts or events 7 VME interrupts VME ACFAIL VME SYSFAIL VME BERR watchdog timer event IRQ11 SCSI or unassigned IRQ12 mouse IRQ13 numeric coprocessor IRQ14 Primary IDE IRQ15 Secondary IDE SMI Power Management INTA PMC1 INTB PMC0 Ethernet INTC SCSI Routed to IRQ11 INTD Universe Bridge Routed to I...

Page 99: ...hannels The assignment of DMA channels for the EPC 9 is shown in the following table Channel Assignment Available on EXM Bus 0 unassigned 8 bit No 1 unassigned 8 bit Yes 2 usually needed for floppy disk 8 bit Yes 3 usually needed for SCSI disk 8 bit Yes 4 Channel 0 Channel 3 cascade through Channel 4 No 5 unassigned 16 bit Yes 6 unassigned 16 bit Yes 7 unassigned 16 bit No Table B 2 DMA Channels A...

Page 100: ...the front panel are shown in Figure C 2 The optional PMC 1 Video Module is shown Your system may or may not include the PMC 1 module depending on ordered options The JP1 header primary EIDE is located under the optional PMC 1 Video Module Pins are labeled from the point of view of looking at the front of the connector Figure C 1 EPC 9 Assembly Artisan Technology Group Quality Instrumentation Guara...

Page 101: ...EPC 9 Hardware Reference C C C 2 Figure C 2 EPC 9 Front Panel Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 102: ...5V 2 not used 5 Clock 3 Ground 6 not used Table C 1 Keyboard Pin Out Mouse Connector The PS 2 mouse connector is a 6 pin mini DIN connector defined as follows Pin Signal Pin Signal 1 Data 4 5V 2 not used 5 Clock 3 Ground 6 not used Table C 2 Mouse Pin Out Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 103: ... Out Parallel Port The LPT1 parallel port female DB 25 connector is defined as follows Pin Signal Pin Signal 1 Strobe 14 Auto line feed 2 DB0 15 Error 3 DB1 16 Initialize printer 4 DB2 17 Select in 5 DB3 18 Signal ground 6 DB4 19 Signal ground 7 DB5 20 Signal ground 8 DB6 21 Signal ground 9 DB7 22 Signal Ground 10 Acknowledge 23 Signal ground 11 Busy 24 Signal ground 12 Paper End 25 Signal ground ...

Page 104: ...13 Horizontal sync 6 Ground 14 Vertical sync 7 Ground 15 programmable 8 Ground output Table C 5 DB 15 Pin Out RJ45 Connector The DTE RJ45 phone jack that supplies the 10Base T 100Base TX interface to the Ethernet controller is defined as follows Pin Signal 1 Tx 2 Tx 3 Rx 4 No connect 5 No connect 6 Rx 7 No connect 8 No connect Table C 6 RJ45 Phone Jack Pin Out Artisan Technology Group Quality Inst...

Page 105: ... stacked 4 pin connector defined as follows Pin Description Mechanical Solder Lug Shield Ground 1 VCC 1Amp Fused 2 DATA 3 DATA 4 Signal Ground Mechanical Solder Lug Shield Ground Table C 7 Dual USB Connector 83 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 106: ...0 Signal GND 6 DB2 31 Signal GND 7 Signal GND 32 ATN 8 DB3 33 Signal GND 9 Signal GND 34 Signal GND 10 DB4 35 Signal GND 11 Signal GND 36 BSY 12 DB5 37 Signal GND 13 Signal GND 38 ACK 14 DB6 39 Signal GND 15 Signal GND 40 RST 16 DB7 41 Signal GND 17 Signal GND 42 MSG 18 DBP 43 Signal GND 19 Signal GND 44 SEL 20 Signal GND 45 Signal GND 21 Signal GND 46 C D 22 Signal GND 47 Signal GND 23 Signal GND...

Page 107: ...ing table Pin Signal Pin Signal 1 RST 2 GND 3 D7 4 D8 5 D6 6 D9 7 D5 8 D10 9 D4 10 D11 11 D3 12 D12 13 D2 14 D13 15 D1 16 D14 17 D0 18 D15 19 GND 20 N C 21 DRQ 22 GND 23 IOW 24 GND 25 IOR 26 GND 27 IORDY 28 PPU 29 DAK 30 GND 31 IRQ 32 IOCS16 33 A1 34 N C 35 A0 36 A2 37 CS0 38 CS1 39 ACT 40 GND 41 Vcc 42 Vcc 43 GND 44 GND Table C 9 Primary EIDE Connector Artisan Technology Group Quality Instrumenta...

Page 108: ...owing table Pin Signal Pin Signal 1 RST 2 GND 3 D7 4 D8 5 D6 6 D9 7 D5 8 D10 9 D4 10 D11 11 D3 12 D12 13 D2 14 D13 15 D1 16 D14 17 D0 18 D15 19 GND 20 N C 21 DRQ 22 GND 23 IOW 24 GND 25 IOR 26 GND 27 IORDY 28 SPU 29 DAK 30 GND 31 IRQ 32 IOCS16 33 A1 34 N C 35 A0 36 A2 37 CS0 38 CS1 39 ACT 40 GND Table C 10 Secondary EIDE Connector Artisan Technology Group Quality Instrumentation Guaranteed 888 88 ...

Page 109: ... 1 GND 2 DENSEL 3 N C 4 N C 5 N C 6 RATE0 7 Vcc 8 INDEX 9 Vcc 10 MTR1 11 Vcc 12 DS0 13 GND 14 DS1 15 GND 16 MTR0 17 GND 18 DIR 19 GND 20 STEP 21 GND 22 WDATA 23 GND 24 WGATE 25 GND 26 TRK0 27 GND 28 WRPRT 29 GND 30 RDATA 31 GND 32 HDSEL 33 GND 34 DSKCHG Vcc if jumper JP2 is installed RadiSys floppy drive N C if jumper JP2 is not installed Table C 11 Floppy Disk Drive Connector Artisan Technology G...

Page 110: ...or Module SCSI Terminator Disable Jumper J11 The SCSI Terminator Disable Jumper J11 is located behind the battery on the Main I O board under the optional PMC1 SVGA Module as shown in Figure C 1 To disable the SCSI terminator apply a jumper to J11 The last module in a SCSI chain must have an active terminator while all other modules must have the terminator disabled The EPC 9 is shipped with the j...

Page 111: ...EPC 9 Hardware Reference C C C 12 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 112: ...e subplanes are designated BP9E0 BP9E2 and BP9E4 and provide zero two and four EXM connectors respectively For systems that have the EXP MX Mass Storage Module the subplanes are designated BP9E0M BP9E2M and BP9E4M and provide zero two and four EXM connectors respectively plus the connector for the EXP MX Mass Storage Module Each subplane is described in the subsections that follow Locate the appro...

Page 113: ...ots Note that no EXM modules or EXP MX Mass Storage Modules can be used with this configuration The BP9E0 is an L shaped board with one connector on the front and three on the back QVWDOO 90 EXV MXPSHUV LQ WKLV VORW QVWDOO WKH 3 LQ WKHVH WZR VORWV Figure D 1 BP9E0 Subplane Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 114: ...ring the backplane plug the subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 9 subsystem will occupy The EXM slot numbers are shown in the drawing Figure D 2 BP9E0M Subplane QVWDOO 90 EXV MXPSHUV LQ WKHVH WKUHH VORWV QVWDOO WKH 3 LQ WKHVH WZR VORWV Artisan Technology Group Quality I...

Page 115: ...plane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 9 subsystem will occupy The EXM slot numbers are shown in the drawing QVWDOO RSWLRQDO 0 PRGXOHV LQ WKHVH WZR KDOI VORWV QVWDOO 90 EXV MXPSHUV LQ WKHVH WZR VORWV QVWDOO WKH 3 LQ WKHVH WZR VORWV Figure D 3 BP9E2 Subplane Artisan Technology...

Page 116: ...subplane into the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 9 subsystem will occupy The EXM slot numbers are shown in the drawing QVWDOO RSWLRQDO 0 PRGXOHV LQ WKHVH WZR KDOI VORWV QVWDOO 90 EXV MXPSHUV LQ WKHVH IRXU VORWV QVWDOO WKH 3 LQ WKHVH WZR VORWV Figure D 4 BP9E2M Subplane Artisan Techn...

Page 117: ...the VMEbus backplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 9 subsystem will occupy The EXM slot numbers are shown in the drawing Figure D 5 BP9E4 Subplane QVWD OO RS WLRQD O 0 P RG XOHV LQ WKHVH IRXU KD OI VORWV QVWD OO 90 E XV MXP S HUV LQ WKHVH WKUHH VORWV QVWD OO WKH 3 LQ WKHVH WZR VORWV Artisan Technol...

Page 118: ...kplane such that the P2 connector on the back of the 4 row DIN is pressed into the J2 connector of the left most VMEbus slot that the EPC 9 subsystem will occupy The EXM slot numbers are shown in the drawing QVWDOO WKH RSWLRQDO 3 0 PRGXOH LQ WKHVH WZR VORWV QVWDOO WKH 3 LQ WKHVH WZR VORWV QVWDOO RSWLRQDO 0 PRGXOHV LQ WKHVH IRXU KDOI VORWV QVWDOO 90 EXV MXPSHUV LQ WKHVH ILYH VORWV Figure D 6 BP9E4M...

Page 119: ...EPC 9 Hardware Reference D D D 8 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 120: ...Register ML 15 8 814Fh Control Register SLOT1 RONR WDTR WDTV 8150h ULA ULA 7 0 8151h VME Event Register 11111 MSGE SIGE WDTE 8152h VME Event Enable Register LRRY LWRY 11 IACK MSGIE SIGIE WDTIE 8153h Status Control Register SRIE 1 SYSC 1 RDY PASS NOSF RSTP 8154h Status Control Register 0 MODI SYSR 1 1 1 1 1 8155h Model Register MODEL 8156h Signal FIFO Low SRFL 8158h Signal FIFO High SRFH 8159h Resp...

Page 121: ...ved 8178h MODID Upper Register MODID 12 5 8179h VXI Register Offsets see VXI Register Base Address Decoding below for base address determination ID ULA Register ECh 0h ID ULA Register 8Fh 1h Device Type Register MM 2h Device Type Register 0001 000S 3h Status Control Register SRIE 1 SYSC 1 RDY PASS NOSF RS TP 4h Status Control Register 0 MODI SYSR 1 1 1 1 1 5h Protocol Low Register FFh 8h Protocol ...

Page 122: ...read or written from VME It serves as a location monitor for determining whether a message is 16 or 32 bits in length Access from the PC port has no effect on ABMH When the low byte of Message Low is read from VME RRY in the Response register is cleared When the low byte of Message Low is written from VME WRY in the Response register is cleared Access from PC port has no effect on RRY and WRY The ...

Page 123: ...to prevent generating an interrupt ULA 8151h ULA 7 0 8151h This register is set to all 1 s by a PCI reset The ULA register is an 8 bit value that represents the Unique Logical Address of the VXI registers This register is driven onto the VME bus D 7 0 during an IACK response cycle VME D 15 8 is driven from the lower 8 bits of the Message Low register ULA is only readable from this port It is writt...

Page 124: ...d to the processor The IACK bit indicates when an interrupt acknowedge is occuring It indicates the actual value of the IACK signal line on the VME bus These bits are a mask of the interrupt conditions in the event state register A one denotes that the corresponding event is enabled as an interrupt If any bit in this register is a one and the corresponding bit in the event state register is a zero...

Page 125: ...n algorithmic fashion SIG FSIG and LSIG are fields in the Response register The signal FIFO SRFIFO is a two element array with indexes A write to the Protocol register from the VXI bus see VXI Register Details below is a write to the signal FIFO and does the following if SIG FSIG LSIG FIFO full Assert BERR else if SIG LSIG LSIG SRFIFO LSIG write data SIG 1 A read from SRFL returns the low order by...

Page 126: ...as asserted IACK Latches 8162h 816Fh IACK Latch 1 Low IACK1 7 0 8162h IACK Latch 1 High IACK1 15 8 8163h IACK Latch 2 Low IACK2 7 0 8164h IACK Latch 2 High IACK2 15 8 8165h IACK Latch 3 Low IACK3 7 0 8166h IACK Latch 3 High IACK3 15 8 8167h IACK Latch 4 Low IACK4 7 0 8168h IACK Latch 4 High IACK4 15 8 8169h IACK Latch 5 Low IACK5 7 0 816Ah IACK Latch 5 High IACK5 15 8 816Bh IACK Latch 6 Low IACK6 ...

Page 127: ...ter adheres to the VXIbus specification It defines EPC 9 as a message based device and the manufacturer as RadiSys When read the ID is returned When written the lower 8 bits define the unique logical address ULA The upper 8 bits are ignored The ULA is not valid as an addressing mechanism until the register is written the first time Until then one must use the MODID address mechanism i e ULA of FFh...

Page 128: ...and PASS 1 EPC 9 is ready to accept VXI defined messages PASS If set 1 EPC 9 has completed its self test successfully If this bit is cleared 0 the Test LED on EPC 9 front panel is lit indicating that self test failed NOSF SYSFAIL inhibit If set 1 EPC 9 will not assert the VME bus SYSFAIL line due to the PASS bit being cleared If the PASS bit is cleared and this bit is cleared 0 then SYSFAIL will b...

Page 129: ...the PC port Note that some of these bits ABMH MLK RRY and WRY can be cleared by hardware when access is made to the message registers from the VME port Software protocols as defined by the VXI specification guarantee that this does not happen at the same time as a write from the PC port to these bits If software violates this protocol unpredictable results will occur LOCK RAM bit available to soft...

Page 130: ...ion protocols RRY Read ready A 1 denotes that the message registers contain outgoing data to be read by another device RRY is cleared when the message low register is read from VME RRY can only be set by writing to this register from the PC port WRY Write ready If set the message registers are armed for an incoming mes sage When a write occurs into the message low register WRY is cleared and the M...

Page 131: ... Alternate Response register is accessed at offset 0x2A from the VME A16 base address of these registers LOCK RRIE MLK ABMH DIR DOR ERR can be set or cleared by using a write to the response register RRY and WRY may only set via a write to the Response register For these two bits a 0 written into the respective bit position will not change the value of the register bit A 1 written into the respect...

Page 132: ...the lower 8 bits at 8151h xxxx xxxx aaaa aaaa 2 Form the base address as 11aa aaaa aa00 0000 where aaaa aaaa are the lower 8 bits at 8151h 3 The result is the binary representation of the VXI Register Base Address 4 Thus the lowest possible base address is C000h 1100 0000 0000 0000 and the highest possible base address is FFC0h 1111 1111 1100 0000 Note that the range consists of base addresses sep...

Page 133: ...EPC 9 Hardware Reference E E E 14 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 134: ...software interface specification that allows operating system device drivers to control the power management functionality of a PC American National Standards Institute ANSI An organization dedicated to advancement of national standards related to product manufacturing AT Bus Attachment ATA An interface definition for PC peripherals See IDE Autotype A convenient method of IDE device detection wher...

Page 135: ...ry A process whereby an existing corrupt BIOS image in the flash boot device is overwritten with a new image Also referred to as a flash recovery BIOS Update A process whereby an existing uncorrupted BIOS image in the flash boot device is overwritten with a new image Also referred to as a flash update Bit A binary digit Boot The process of starting a computer and loading the operating system from ...

Page 136: ...as many pins to define an address location in a DRAM device as would otherwise be required COM Port A bi directional serial communication port which implements the RS 232 specification Complimentary Metal Oxide Semiconductor CMOS A fast low power semiconductor RAM used to store system configuration data Conventional Memory The first 640 KB of a computer s total memory capacity If a computer has no...

Page 137: ...cess Memory DRAM Semiconductor RAM memory devices in which the stored data will not remain permanently stored even with the power applied unless the data are periodically rewritten into memory during a refresh operation E Electrically Erasable Programmable ROM EEPROM Specifically those EPROMs which may be erased electrically as compared to other erasing methods Error Checking and Correction A feat...

Page 138: ...e and other popular mass storage technologies Field Programmable Gate Array FPGA A large general purpose logic device that is programmed at power up to perform specific logic functions Flash Boot Device FBD A flash memory device containing the computer s BIOS In the EPC 9 a 512 KB Intel 28F004BV T semiconductor flash memory containing the system and video BIOS images the BIOS initializing code and...

Page 139: ...he communication interface between system components and between the system and connected peripherals Integrated Drive Electronics IDE A hard disk drive controller interface standard IDE drives contain the controller circuitry at the drive itself as compared to the location of this circuitry on the computer motherboard in non IDE systems IDE drives typically connect to the system bus with a simple...

Page 140: ...tes 2 10 1024 bytes exactly L Logical Address The memory mapped location of a segment after application of the address offset to the physical address Logical Block Addressing LBA A method the system BIOS uses to reference hard disk data as logical blocks with each block having a specific location on the disk LBA differs from the CHS reference method in that the BIOS requires no information relatin...

Page 141: ...back control system to maintain a closely regulated output frequency from an unregulated input frequency The typical PLL consists of an internal phase comparator or detector a low pass filter and a voltage controlled oscillator which function together to capture and lock onto an input frequency When locked onto the input frequency the PLL can maintain a stable regulated output frequency within bou...

Page 142: ...conductor memories designed for applications where the ratio of read operations to write operations is very high Technically a ROM can be written to programmed only once and this operation is normally performed at the factory Thereafter information can be read from the memory indefinitely Real Mode The operational mode of Intelx86 CPUs that uses a segmented offset memory addressing method These CP...

Page 143: ...e data The DRAM requires a row address and a column address to define a memory address Since both parts of the address are applied at the same DRAM inputs use of row addresses and column addresses in a multiplexed array allows use of half as many pins to define an address location in a DRAM device as would otherwise be required S Segment A section or portion of addressable memory serving to hold c...

Page 144: ...tor RAM device in which the data will remain permanently stored as long as power is applied without the need for periodically rewriting the data into memory Symmetrically Addressable SIMM A SIMM the memory content of which is configured as two independent banks Each 16 bit wide bank contains an equal number of rows and columns and is independently addressable by the CPU via twin row address strobe...

Page 145: ...ly set up the drive for use with the system V Video Electronics Standards Association VESA A group of hardware and software vendors that define specifications for hardware and software interfaces for a variety of devices Video Graphics Adapter VGA A popular PC graphics controller and display adapter standard developed by IBM The standard specifies among other things the resolution capabilities of ...

Page 146: ...roller connected to the 33MHz PCI bus to give the best possible graphics performance The PMC 1 conforms to the PC Mezzanine Card IEEE P1386 form factor The available resolution depends upon the amount of installed memory Table G 1 shows the available resolutions Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 147: ... 800x600 16 4 512KB 800x600 256 8 512KB 800x600 32K 15 8 1MB 800x600 64K 16 1MB 800x600 16M 24 2MB 800x600 16M 32 2MB 1024x768 16 4 512KB 1024x768 256 8 1MB 1024x768 32K 15 8 2MB 1024x768 64K 16 2MB 1024x768 16M 24 2MB 1280x1024 16 4 1MB 1280x1024 256 8 2MB Table G 1 Video Resolutions Available Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 148: ...ocedure 2 Locate the package containing 4 small screws and an O ring It came with the PMC 1 The screws will be used to mount the PMC 1 to the EPC 9 Carrier Board The O ring will be used to seal the PMC 1 Front Panel into the PMC0 opening in the EPC 9 Front Panel 3 Locate and remove the two screws that secure the front panel to the PMC 1 circuit board Remove the two jack screws that attach the fron...

Page 149: ...ving the 6 jack screws 2 each at the COM A COM B and LPT1 connectors Then remove the 2 long screws nuts and sleeves that attach the VME ejector handles 6 Remove the three screws that secure the EPC 9 Carrier Board to the EPC 9 Main Board Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 150: ... the screws mentioned in step 2 to secure the PMC 1 Front Panel to the Carrier Board Be sure to mount the Front Panel so that the opening for the VGA connector is located at the lower side of the EPC 9 Front Panel opening labeled PMC0 Figure G 2 SVGA Module Installation Steps 5 and 6 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 151: ...nto the front panel lugs and the standoffs 12 Install the O ring in the groove in the PMC 1 Front Panel 13 Re install the EPC 9 Front Panel by sliding it carefully over the PMC 1 Front Panel O ring and the O ring in the blank panel 14 Install the 6 jack screws you removed in step 5 and the two jack screws you removed in step 3 15 Install the 2 long screws nuts and sleeves you removed in step 6 Dis...

Page 152: ...ailable from Cirrus Logic support They maintain a web page at http www cirrus com support Also if you need answers to questions about the Cirrus chip you can contact them at e mail ui support corp cirrus com phone 510 623 8300 or FAX 510 252 6020 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 153: ...EPC 9 Hardware Reference G G G 8 Notes Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 154: ...n it encounters the following error conditions 1 Fixed disk error No drive connected Configured for 0 cylinders Controller reset failed Drive not ready Track 0 seek timed out Drive initialization failed Drive recalibration failed Last track seek failed Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 155: ...error Floppy type does not match setup 5 I O chip error I O conflicts exist for serial and parallel ports floppy hard disk any or all 6 Other errors IRQ conflict unsupported COM port configuration keyboard locked Pentium cooling fan failure Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 156: ...ithout onboard video If EXM based video is used the EPC 9 cannot talk to EXM expansion interface Remove the EXM based video adapter if used If the subplane is secured to the VMEbus backplane by retaining screws verify that the subplane is not warped from over tightening the screws Re insert the video adapter and verify proper seating into the subplane Verify that the cable pins are not bent and th...

Page 157: ... in sockets This cannot be diagnosed in the field Call RadiSys Technical Support Serial port s do not work Bad power Interrupt conflicts Port hardware failure Verify that backplane 12V and 12V are good An EXM module is using the same interrupts as COM1 and or COM2 Verify that no other card in the EPC 9 subsystem is using IRQ3 or IRQ4 Call RadiSys Technical Support System hangs during boot process ...

Page 158: ... interface failure See the section Installing the VMEbus Backplane Jumpers in Chapter 2 Determine that the controller is in the left most position and that the Slot 1 controller jumper is set Remove the EPC 9 and the subplane and verify that no pins are bent Then reinsert the subplane and the EPC 9 Call RadiSys Technical Support Table H 1 Troubleshooting Error Messages Artisan Technology Group Qua...

Page 159: ...urs you should contact your supplier for technical support Beep Pattern Condition 1 short POST OK 2 short POST error such as EXM configuration or keyboard error Refer to the message on the screen to determine the cause one long two short Insert BIOS update disk now one long three short Video memory error 3 short BIOS update disk missing Either insert the BIOS update disk or turn the system off and...

Page 160: ... 6 BG0In BG3In 2 4 5 6 BG0Out BG3Out 2 4 5 6 big endian 4 16 4 18 BIOS F 1 setup 3 1 3 34 update 3 33 BIOS Data Area F 2 BIOS extension term defined F 2 BIOS extensions 2 2 3 17 5 6 BIOS Recovery term defined F 2 BIOS setup 4 16 BIOS Update term defined F 2 Block Diagram 4 3 Boot Block term defined F 2 Boot Delay 3 12 Boot device term defined F 2 Boot Options Sub Menu 3 12 Boot Sequence 3 12 defin...

Page 161: ...defined F 3 Coprocessor Interface I O Map A 3 Counter Timer functions I O Map A 1 Ctrl Alt Del 4 15 Current 1 8 Cylinders Heads Sectors CHS term defined F 3 D D08 4 17 D16 4 17 4 18 D32 4 17 daisy chain 2 2 5 6 daisy chain lines 2 3 5 6 DB 25 C 4 DB 9 C 4 Diskette Controller enable disable 3 19 Display Drivers and Utilities G 6 DMA Aliasing 3 21 DMA Aliasing 3 21 DMA channels 3 29 B 2 DMA controll...

Page 162: ...lash Update term defined F 5 floating point numbers 4 18 Floppy Controller 4 12 floppy disk drive connector C 10 floppy drive enable disable search 3 13 front panel LEDs 4 14 G Glossary of Terms F 1 H hard disk transfer mode 3 8 hardware reset 4 15 Header term defined F 6 Humidity 1 7 I I O addresses 3 29 I O Map Coprocessor Interface A 3 counter timer A 1 DMA controller A 1 A 3 ECP Registers A 6 ...

Page 163: ...terrupt E 4 E 5 J J1 connector 2 6 J10 C 11 J11 C 11 jumper 2 3 2 4 5 6 Fan Failure Detect Enable C 11 SCSI Terminator Disable C 11 jumpers 2 5 2 6 backplane 2 4 term defined F 7 K Key Click 3 14 keyboard 2 9 5 6 wake up events 3 26 Keyboard auto repeat rate 3 15 Keyboard auto repeat delay 3 15 Keyboard auto repeat rate specifying 3 15 keyboard connector C 3 Keyboard Features Sub Menu 3 14 Keyboar...

Page 164: ...ng System term defined F 8 Option Byte 3 28 P P2 4 16 Parallel I O LPT1 Port I O Map A 4 Parallel port 3 29 4 11 C 4 PC AT bus D 1 PCI VME Bridge 4 12 PCIbus Access to Universe Registers 5 5 Peripheral Ports 4 10 peripherals 2 3 2 9 5 6 Phoenix NuBIOS 3 1 I O Map A 2 Physical Address term defined F 8 Plug and Play 3 17 I O Map A 4 Plug and Play 4 6 PMC 1 Video Module 4 13 G 1 Port A I O Map A 2 PO...

Page 165: ...ermination 2 9 SCSI terminator C 7 SCSI Terminator Disable Jumper C 11 SCSI 2 C 7 Secondary EIDE C 9 selftest E 9 Serial I O COM A Port I O Map A 5 Serial I O COM B Port I O Map A 4 serial port C 4 Servant E 10 Setup Prompt 3 13 Setup screen 3 1 3 34 shadowing 4 8 Shock 1 7 Signal register E 10 Signal register FIFO E 4 E 10 Single In Line Memory Module SIMM term defined 2 4 5 6 F 11 Slot Numbering...

Page 166: ... VXI Registers in VME Address Space I O Map A 6 Unique Logical Address 3 31 Universal Serial Bus 4 11 Universe as system controller 5 1 programming 5 1 USB 4 11 C 6 User Editable Drive UED term defined F 12 V VGA I O Map A 5 term defined F 12 VGA BIOS 3 10 cacheing 3 10 Vibration 1 7 video 2 9 5 6 options 3 4 video BIOS 4 5 video resolution G 2 VME and Misc I O Map A 6 VME chassis 2 7 5 6 VME even...

Page 167: ...ddress decoding E 13 VXI Register Details E 8 W Wakeup events 3 26 warm boot 4 15 warm reset 4 6 warranty information 6 2 watchdog timer halt on reset 3 17 watchdog timer 4 5 E 4 world wide web technical support 6 1 Write ready E 11 Artisan Technology Group Quality Instrumentation Guaranteed 888 88 SOURCE www artisantg com ...

Page 168: ...l service in house repair center WE BUY USED EQUIPMENT Sell your excess underutilized and idle used equipment We also offer credit for buy backs and trade ins www artisantg com WeBuyEquipment REMOTE INSPECTION Remotely inspect equipment before purchasing with our interactive website at www instraview com LOOKING FOR MORE INFORMATION Visit us on the web at www artisantg com for more information on ...

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