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EPC-9 Hardware Reference
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allow the boot process to continue. At this point, the software may de-assert VME
SYSFAIL* by reading 8150h.
Note that a watchdog hardware reset results in a "warm" hardware reset. A warm
hardware reset clears all register bits except for the upper four bits of the
Configuration register (these control slot1 arbitration functions) and bit 4 and 6 of the
Module Status/Control register. Bit 4 enables the VME bus time-out function and bit 6
enables asserting VME SYSRESET*, if set. A warm reset does clear WDTR (bit 0 of
the Module Status) to allow the hardware to be released from the warm reset state,
but SYSFAIL will continue to be driven until the WDT bit is cleared by either
reading the Module Status/Control Register or by a power-on reset.
If WDTR is clear, WDT mask (bit 0 of register 8153h) enables an interrupt if a time-
out event occurs (SYSFAIL is not driven). The clock input to the counter is disabled
if the interrupt is pending and not serviced. Service of the interrupt is signaled to the
counter by reading register 8150h. This will reset the counter value and resume
counting. The interrupt is signaled on IRQ10. The timer event also clears WDT bit in
the VME event register (bit 0 of register 8153h).
Application software that utilizes this timer should take care to reset the counter just
prior to enabling the interrupt bit in register 8155h. This will inhibit a spurious timer
event from occurring just after enabling the timer.
Flash Boot Device
The Intel E28F004BX-T is used as a Flash Boot Device (FBD). This is flash-
updatable BIOS containing the boot, main, and parameter blocks shown in Figure 4-2
and shadowed at the top of 32-bit address space. The use of the FBD allows
reprogramming of the main and parameter blocks of the BIOS.
The Plug-and-Play ESCD is also stored in the Boot-Block FLASH device in the block
addressed from FFFA0000h-FFFBFFFFh. This block is always accessible for re-
programming.
The boot block is NEVER reprogrammed by the user, even when the main and
parameter blocks are reprogrammed. The capability to program the boot block is
provided to facilitate changes by RadiSys manufacturing.
A “ forced recovery” jumper is provided that is connected to the P1-3 input of the
82C4PE keyboard controller. This jumper is readable by the boot block and can force
the boot block to initiate a recovery sequence at power-up should other methods of
initiating the sequence become inaccessible. (i.e. crisis recovery)
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