Theory of Operation
4
4
4-5
Memory Map
The 2
32
byte physical address space seen by the Intel Pentium occupies three areas:
1.
The area between 0 and 1 MB is largely defined by the IBM PC/AT
architecture.
2.
The area between 1 MB and 256 MB depends on how much DRAM is
installed in the EPC-9.
3.
The area above 256 MB, provides direct mapping to the VMEbus with a
variety of address modifiers and byte orderings.
Memory at addresses between 0 and 1 MB (0FFFFFh) is mapped as follows:
Range
Content
000000 - 09FFFF
First 640 KB of DRAM (DOS memory)
0A0000 - 0BFFFF
VGA video DRAM, mapped to the PMC-1
Video Module
0C0000 - 0C7FFF
Write-protected DRAM containing shadowed
video BIOS
0C8000 - 0CFFFF
SCSI BIOS extension
0D0000 - 0DFFFF
EXMbus
0E0000 - 0E3FFF
Universe bridge registers
0E4000 - 0FFFFF
Shadowed system BIOS
Watchdog Timer
The watchdog timer is a binary counter which, upon overflow, will signal a watchdog
timer event. The counter will cause a watchdog event after approximately 125 ms, 1
second or 8 seconds (depending on the value of WDTV, bits 2 and 1 in register
8150h) if the application software does not reset the timer.
An I/O read to address 8150h resets the counter. If WDTR (bit 3 of register 815Dh) is
set, the following occurs in response to a timeout event:
WDT (bit 0 of register 8153h) is set. A local “ warm” hardware reset occurs and
VME SYSFAIL* is asserted. When exiting a hardware reset event, the BIOS checks
the condition of WDT. If WDT is set (0), then a watchdog timeout caused the
hardware reset. Then, depending on whether the "Halt on watchdog reset" option of
the Advanced BIOS Setup menu is enabled, the BIOS will either HALT the CPU or
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